This is a two-part thesis.Part-I: This work investigated the long-term reliability of a statistically significant number of two different commercial module-level power electronics (MLPE) devices using two input power profiles at high temperatures to estimate their reliability and service life in field-use conditions. Microinverters underwent a period of 15,000 accelerated stress hours, whereas the power optimizers underwent a period of 6,400 accelerated stress hours. None of the MLPE devices failed during the accelerated test; however, the optimizers degraded by about 1% in output efficiency. Based on their accelerated stress temperatures, the estimated field equivalent service life approximated using the Arrhenius model ranges between 24-48 years for microinverters and 39-73 years for optimizers, with a reliability of 74% and a lower one-sided confidence level of 95%. Furthermore, using the Weibull distribution model, the reliability and service lifetimes of MLPE devices are statistically analyzed. MLPE lifetimes estimated using Weibull slope and shape parameters with a 95% lower one-sided confidence level indicate a similar, or possibly exceeding, the 25-year lifetime of the associated photovoltaic (PV) modules. Part–II:This study investigated the impact of the hotspot stress test on glass-backsheet and glass-glass modules. Before the hotspot testing, both modules were pre-stressed using 600 thermal cycles (TC600) to represent decades of field-exposed modules experiencing hotspot effects in field-use conditions. The glass-glass module reached a hotspot temperature of nearly 200°C, whereas the glass-backsheet module's maximum hotspot temperature was almost 150°C. After the hotspot experiment, electroluminescence imaging showed that most of the cells in the glass-glass module appeared to have experienced significant damage. In contrast, the stressed cells in the glass-backsheet module appeared to have experienced insignificant damage. After the sequential stress testing (hotspot testing after TC600), the glass-glass module degraded by nearly 8.3% in maximum power, whereas the glass-backsheet module experienced 1.3% degradation. This study also incorporated hotspot endurance in fresh (without being subjected to prior TC600) glass-glass and glass-backsheet modules. The test outcome demonstrated that both module types exhibited marginal maximum power loss.

A photovoltaic (PV) module is a series and parallel connection of multiple PV cells; defects in any cell can cause module power to drop. Similarly, a photovoltaic system is a series and parallel connection of multiple modules, and any low-performing module in the PV system can decrease the system output power. Defects in a solar cell include, but not limited to, the presence of cracks, potential induced degradation (PID), delamination, corrosion, and solder bond degradation. State-of-the-art characterization techniques to identify the defective cells in a module and defective module in a string are i) Current-voltage (IV) curve tracing, ii) Electroluminescence (EL) imaging, and iii) Infrared (IR) imaging. Shortcomings of these techniques include i) unsafe connection and disconnection need to be made with high voltage electrical cables, and ii) labor and time intensive disconnection of the photovoltaic strings from the system.This work presents a non-contact characterization technique to address the above two shortcomings. This technique uses a non-contact electrostatic voltmeter (ESV) along with a probe sensor to measure the surface potential of individual solar cells in a commercial module and the modules in a string in both off-grid and grid-connected systems. Unlike the EL approach, the ESV setup directly measures the surface potential by sensing the electric field lines that are present on the surface of the solar cell. The off-grid testing of ESV on individual cells and multicells in crystalline silicon (c-Si) modules and on individual cells in cadmium telluride (CdTe) modules and individual modules in a CdTe string showed less than 2% difference in open circuit voltage compared to the voltmeter values. In addition, surface potential mapping of the defective cracked cells in a multicell module using ESV identified the dark, grey, and bright areas of EL images precisely at the exact locations shown by the EL characterization. The on-grid testing of ESV measured the individual module voltages at maximum power point (Vmpp) and quantitatively identified the exact PID-affected module in the entire system. In addition, the poor-performing non-PID modules of a grid-connected PV system were also identified using the ESV technique.

Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.

The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.

The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.

A wideband hybrid envelope tracking modulator utilizing a hysteretic-controlled three-level switching converter and a slew-rate enhanced linear amplifierer is presented. In addition to smaller ripple and lower losses of three-level switching converters, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage VCF and eliminates conventional required calibration loop to control it. The hysteretic-controlled three-level switching converter provides a high percentage of power amplifier supply load current with lower ripple, reducing the linear amplifier high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the linear amplifier resulting in slew-rate of

over 307V/us and bandwidth of over 275MHz for the linear amplifier. The slew-rate enhancement circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of out-

put without modifying the operating point of the remaining linear amplifier, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in 65nm CMOS process. The measurement results show the tracking of LTE-40MHz envelope with 93% peak efficiency at 1W output power, while the SRE is disabled. Enabling the SRE it can track LTE-80MHz envelope with peak efficiency of 91%.

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:

1) A transformer-based power combiner architecture for out-phasing transmitters

2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)

3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters

This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.

The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.

Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.

There is an increasing demand for fully integrated point-of-load (POL) isolated DC-DC converters that can provide an isolation barrier between the primary and the secondary side, while delivering a low ripple, low noise regulated voltage at their isolated sides to a high dynamic range, sensitive mixed signal devices, such as sensors, current-shunt-monitors and ADCs. For these applications, smaller system size and integration level is important because the whole system may need to fit to limited space. Traditional methods for providing isolated power are discrete solutions using bulky transformers. Miniaturization of isolated POL regulators is becoming highly desirable for low power applications.

A fully integrated, low noise isolated point-of-load DC-DC converter for supply regulation of high dynamic range analog and mixed signal sensor signal-chains is presented. The isolated DC-DC converter utilizes an integrated planar air-core micro-transformer as a coupled resonator and isolation barrier and enables direct connection of low-voltage mixed signal circuits to higher supply rails. The air core transformer is driven at its primary resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The isolated converter’s output ripple is reduced by utilizing spread spectrum clocking in the driver. An isolated PMOS LDO in the secondary side is used to suppress switching noise and ripple by 21dB. Conducted and radiated EMI distribution on the IC is measured by a set of integrated ring oscillator based noise sensors with -68dBm noise sensitivity. The proposed isolated converter achieves highest level of integration with respect to earlier reported integrated isolated converters, while providing 50V on-chip junction isolation without the need for extra silicon post-processing steps.

The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world.

Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels.

Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application.

In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency.

The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.

In this work, the development of a novel and a truly in-shoe force measurement system is reported. The device consists of a shoe insole with six thin film piezoresistive sensors and the main circuit board. The piezoresistive sensors are used for the measurement of plantar pressure during daily human activities. The motion sensor mounted on the main circuit board captures kinematic data. In addition, the main circuit board is responsible for the wireless transmission of the data from all the sensors in real-time using BLE protocol. It is housed within the midsole of the shoe, under the medial arch of the foot. The real-time quantitative data and its analyses, enables athletic performance evaluation, biomedical ailment detection, and everyday fitness tracking. A test subject walked 20 steps on a flat surface at a comfortable speed wearing a shoe fitted with the insole and the main circuit board. Measurements were captured using a BLE enabled laptop and the test results were validated for accuracy. From the real-time data captured, the number of steps walked, the speed and the plantar pressure applied can be clearly established. Moreover, additional kinematic data from the motion sensor was captured. Further processing of kinematic data using techniques such as machine learning is essential to get meaningful inferences.

The demand for the higher data rate in the wireless telecommunication is increasing rapidly. Providing higher data rate in cellular telecommunication systems is limited because of the limited physical resources such as telecommunication frequency channels. Besides, interference with the other users and self-interference signal in the receiver are the other challenges in increasing the bandwidth of the wireless telecommunication system.

Full duplex wireless communication transmits and receives at the same time and the same frequency which was assumed impossible in the conventional wireless communication systems. Full duplex wireless communication, compared to the conventional wireless communication, doubles the channel efficiency and bandwidth. In addition, full duplex wireless communication system simplifies the reusing of the radio resources in small cells to eliminate the backhaul problem and simplifies the management of the spectrum. Finally, the full duplex telecommunication system reduces the costs of future wireless communication systems.

The main challenge in the full duplex wireless is the self-interference signal at the receiver which is very large compared to the receiver noise floor and it degrades the receiver performance significantly. In this dissertation, different techniques for the antenna interface and self-interference cancellation are proposed for the wireless full duplex transceiver. These techniques are designed and implemented on CMOS technology. The measurement results show that the full duplex wireless is possible for the short range and cellular wireless communication systems.