An efficient thermal solver is available in the CMC that allows modeling self-heating in the electrical simulations, which treats phonons as flux and solves the energy balance equation to quantify thermal effects. Using this solver, thermal simulations were performed on GaN-HEMTs in order to test effect of gate architectures on the DC and RF performance of the device. A Π- gate geometry is found to suppress 19.75% more hot electrons corresponding to a DC power of 2.493 W/mm for Vgs = -0.6V (max transconductance) with respect to the initial T-gate. For the DC performance, the output current, Ids is nearly same for each device configuration over the entire bias range. For the RF performance, the current gain was evaluated over a frequency range 20 GHz to 120 GHz in each device for both thermal (including self-heating) and isothermal (without self-heating). The evaluated cutoff frequency is around 7% lower for the thermal case than the isothermal case. The simulated cutoff frequency closely follows the experimental cutoff frequency. The work was extended to the study of ultra-wide bandgap material (Diamond), where isotope effect causes major deterioration in thermal conductivity. In this case, bulk phonons are modeled as semiclassical particles solving the nonlinear Peierls - Boltzmann transport equation with a stochastic approach. Simulations were performed for 0.001% (ultra-pure), 0.1% and 1.07% isotope concentration (13C) of diamond, showing good agreement with the experimental values. Further investigation was performed on the effect of isotope on the dynamics of individual phonon branches, thermal conductivity and the mean free path, to identify the dominant phonon branch. Acoustic phonons are found to be the principal contributors to thermal conductivity across all isotope concentrations with transverse acoustic (TA2) branch is the dominant branch with a contribution of 40% at room temperature and 37% at 500K. Mean free path computations show the lower bound of device dimensions in order to obtain maximum thermal conductivity. At 300K, the lowest mean free path (which is attributed to Longitudinal Optical phonon) reduces from 24nm to 8 nm for isotope concentration of 0.001% and 1.07% respectively. Similarly, the maximum mean free path (which is attributed to Longitudinal Acoustic phonon) reduces from 4 µm to 3.1 µm, respectively, for the same isotope concentrations. Furthermore, PETSc (Portable, Extensible Toolkit for Scientific Computation) developed by Argonne National Lab, was included in the existing Cellular Monte Carlo device simulator as a Poisson solver to further extend the capability of the simulator. The validity of the solver was tested performing 2D and 3D simulations and the results were compared with the well-established multigrid Poisson solver.

In the last few decades, extensive research efforts have been focused on scaling down silicon-based complementary metal-oxide semiconductor (CMOS) technology to enable the continuation of Moore’s law. State-of-art CMOS includes fully depleted silicon-on-insulator (FDSOI) field-effect-transistors (FETs) with ultra-thin silicon channels (6 nm), as well as other three-dimensional (3D) device architectures like Fin-FETs, nanosheet FETs, etc. Significant research efforts have characterized these technologies towards various applications, and at different conditions including a wide range of temperatures from room temperature (300 K) down to cryogenic temperatures. Theoretical efforts have studied ultrascaled devices using Landauer theory to further understand their transport properties and predict their performance in the quasi-ballistic regime.Further scaling of CMOS devices requires the introduction of new semiconducting channel materials, as now established by the research community. Here, two-dimensional (2D) semiconductors have emerged as a promising candidate to replace silicon for next-generation ultrascaled CMOS devices. These emerging 2D semiconductors also have applications beyond CMOS, for example in novel memory, neuromorphic, and spintronic devices. Graphene is a promising candidate for spintronic devices due to its outstanding spin transport properties as evidenced by numerous studies in non-local lateral spin valve (LSV) geometries. The essential components of graphene-based LSV, such as graphene FETs, metal-graphene contacts, and tunneling barriers, were individually investigated as part of this doctoral dissertation. In this work, several contributions were made to these CMOS and beyond CMOS technologies. This includes comprehensive characterization and modeling of FDSOI nanoscale FETs from room temperature down to cryogenic temperatures. Using Landauer theory for nanoscale transistors, FDSOI devices were analyzed and modeled under quasi-ballistic operation. This was extended towards a virtual-source modeling approach that accounts for temperature-dependent quasi-ballistic transport and back-gate biasing effects. Additionally, graphene devices with ultrathin high-k gate dielectrics were investigated towards FETs, non-volatile memory, and spintronic devices. New contributions were made relating to charge trapping effects and their impact on graphene device electrostatics (Dirac voltage shifts) and transport properties (impact on mobility and conductivity). This work also studied contact resistance and tunneling effects using transfer length method (TLM) graphene FET structures and magnetic tunneling junction (MTJ) towards graphene-based LSV.

Wide Bandgap (WBG) semiconductor materials are shaping day-to-day technologyby introducing powerful and more energy responsible devices. These materials have opened the door for building basic semiconductor devices which are superior in terms of handling high voltages, high currents, power, and temperature which is not possible using conventional silicon technology. As the research continues in the field of WBG based devices, there is a potential chance that the power electronics industry can save billions of dollars deploying energy-efficient circuits in high power conversion electronics. Diamond, silicon carbide and gallium nitride are the top three contenders among which diamond can significantly outmatch others in a variety of properties. However, diamond technology is still in its early phase of development and there are challenges involved in many aspects of processing a successful integrated circuit. The work done in this research addresses three major aspects of problems related to diamond technology. In the first part, the applicability of compact modeling and Technology Computer-Aided Design (TCAD) modeling technique for diamond Schottky p-i-n diodes has been demonstrated. The compact model accurately predicts AC, DC and nonlinear behavior of the diode required for fast circuit simulation. Secondly, achieving low resistance ohmic contact onto n-type diamond is one of the major issues that is still an open research problem as it determines the performance of high-power RF circuits and switching losses in power converters circuits. So, another portion of this thesis demonstrates the achievement of very low resistance ohmic contact (~ 10-4 Ω⋅cm2) onto n-type diamond using nano crystalline carbon interface layer. Using the developed TCAD and compact models for low resistance contacts, circuit level predictions show improvements in RF performance. Lastly, an initial study of breakdown characteristics of diamond and cubic boron nitride heterostructure is presented. This study serves as a first step for making future transistors using diamond and cubic boron nitride – a very less explored material system in literature yet promising for extreme circuit applications involving high power and temperature.

Over the past few years, research into the use of doped diamond in electronics has seen an exponential growth. In the course of finding ways to reduce the contact resistivity, nanocarbon materials have been an interesting focus. In this work, the transfer length method (TLM) was used to investigate Ohmic contact properties using the tri-layer stack Ti/Pt/Au on nitrogen-doped n-type conducting nano-carbon (nanoC) layers grown on (100) diamond substrates. The nanocarbon material was characterized using Secondary Ion Mass Spectrometry (SIMS), Scanning electron Microscopy (SEM) X-ray diffraction (XRD), Raman scattering and Hall effect measurements to probe the materials characteristics. Room temperature electrical measurements were taken, and samples were annealed to observe changes in electrical conductivity. Low specific contact resistivity values of 8 x 10^-5 Ωcm^2 were achieved, which was almost two orders of magnitude lower than previously reported values. The results were attributed to the increased nitrogen incorporation, and the presence of electrically active defects which leads to an increase in conduction in the nanocarbon. Further a study of light phosphorus doped layers using similar methods with Ti/Pt/Au contacts again yielded a low contact resistivity of about 9.88 x 10^-2 Ωcm^2 which is an interesting prospect among lightly doped diamond films for applications in devices such as transistors. In addition, for the first time, hafnium was substituted for Ti in the contact stack (Hf/Pt/Au) and studied on nitrogen doped nanocarbon films, which resulted in low contact resistivity values on the order of 10^-2 Ωcm^2. The implications of the results were discussed, and recommendations for improving the experimental process was outlined. Lastly, a method for the selective area growth of nanocarbon was developed and studied and the results provided an insight into how different characterizations can be used to confirm the presence of the nanocrystalline diamond material, the limitations due to the film thickness was explored and ideas for future work was proposed.

This creative project is an extension of the work being done as part of Senior Design in<br/>developing the See-Through Car Pillar, a system designed to render the forward car pillars in a car<br/>invisible to the driver so they can have an unobstructed view utilizing displays, sensors, and a<br/>computer. The first half of the paper provides the motivation, design and progress of the project, <br/>while the latter half provides a literature survey on current automobile trends, the viability of the<br/>See-Through Car Pillar as a product in the market through case studies, and alternative designs and <br/>technologies that also might address the problem statement.

Developing countries suffer from various health challenges due to inaccessible medical diagnostic laboratories and lack of resources to establish new laboratories. One way to address these issues is to develop diagnostic systems that are suitable for the low-resource setting. In addition to this, applications requiring rapid analyses further motivates the development of portable, easy-to-use, and accurate Point of Care (POC) diagnostics. Lateral Flow Immunoassays (LFIAs) are among the most successful POC tests as they satisfy most of the ASSURED criteria. However, factors like reagent stability, reaction rates limit the performance and robustness of LFIAs. The fluid flow rate in LFIA significantly affect the factors mentioned above, and hence, it is desirable to maintain an optimal fluid velocity in porous media.

The main objective of this study is to build a statistical model that enables us to determine the optimal design parameters and ambient conditions for achieving a desired fluid velocity in porous media. This study mainly focuses on the effects of relative humidity and temperature on evaporation in porous media and the impact of geometry on fluid velocity in LFIAs. A set of finite element analyses were performed, and the obtained simulation results were then experimentally verified using Whatman filter paper with different geometry under varying ambient conditions. Design of experiments was conducted to estimate the significant factors affecting the fluid flow rate.

Literature suggests that liquid evaporation is one of the major factors that inhibit fluid penetration and capillary flow in lateral flow Immunoassays. The obtained results closely align with the existing literature and conclude that a desired fluid flow rate can be achieved by tuning the geometry of the porous media. The derived statistical model suggests that a dry and warm atmosphere is expected to inhibit the fluid flow rate the most and vice-versa.

This dissertation focuses on three different efficiency enhancement methods that are applicable to handset applications. These proposed designs are based on three critical requirements for handset application: 1) Small form factor, 2) CMOS compatibility and 3) high power handling. The three presented methodologies are listed below:

1) A transformer-based power combiner architecture for out-phasing transmitters

2) A current steering DAC-based average power tracking circuit for on-chip power amplifiers (PA)

3) A CMOS-based driver stage for GaN-based switched-mode power amplifiers applicable to fully digital transmitters

This thesis highlights the trends in wireless handsets, the motivates the need for fully-integrated CMOS power amplifier solutions and presents the three novel techniques for reconfigurable and digital CMOS-based PAs. Chapter 3, presents the transformer-based power combiner for out-phasing transmitters. The simulation results reveal that this technique is able to shrink the power combiner area, which is one of the largest parts of the transmitter, by about 50% and as a result, enhances the output power density by 3dB.

The average power tracking technique (APT) integrated with an on-chip CMOS-based power amplifier is explained in Chapter 4. This system is able to achieve up to 32dBm saturated output power with a linear power gain of 20dB in a 45nm CMOS SOI process. The maximum efficiency improvement is about ∆η=15% compared to the same PA without APT. Measurement results show that the proposed method is able to amplify an enhanced-EDGE modulated input signal with a data rate of 70.83kb/sec and generate more than 27dBm of average output power with EVM<5%.

Although small form factor, high battery lifetime, and high volume integration motivate the need for fully digital CMOS transmitters, the output power generated by this type of transmitter is not high enough to satisfy the communication standards. As a result, compound materials such as GaN or GaAs are usually being used in handset applications to increase the output power. Chapter 5 focuses on the analysis and design of two CMOS based driver architectures (cascode and house of cards) for driving a GaN power amplifier. The presented results show that the drivers are able to generate ∆Vout=5V, which is required by the compound transistor, and operate up to 2GHz. Since the CMOS driver is expected to drive an off-chip capacitive load, the interface components, such as bond wires, and decoupling and pad capacitors, play a critical role in the output transient response. Therefore, extensive analysis and simulation results have been done on the interface circuits to investigate their effects on RF transmitter performance. The presented results show that the maximum operating frequency when the driver is connected to a 4pF capacitive load is about 2GHz, which is perfectly matched with the reported values in prior literature.

In this work, an advanced simulation study of reliability in millimeter-wave (mm-wave) GaN Devices for power amplifier (PA) applications is performed by means of a particle-based full band Cellular Monte Carlo device simulator (CMC). The goal of the study is to obtain a systematic characterization of the performance of GaN devices operating in DC, small signal AC and large-signal radio-frequency (RF) conditions emphasizing on the microscopic properties that correlate to degradation of device performance such as generation of hot carriers, presence of material defects and self-heating effects. First, a review of concepts concerning GaN technology, devices, reliability mechanisms and PA design is presented in chapter 2. Then, in chapter 3 a study of non-idealities of AlGaN/GaN heterojunction diodes is performed, demonstrating that mole fraction variations and the presence of unintentional Schottky contacts are the main limiting factor for high current drive of the devices under study. Chapter 4 consists in a study of hot electron generation in GaN HEMTs, in terms of the accurate simulation of the electron energy distribution function (EDF) obtained under DC and RF operation, taking into account frequency and temperature variations. The calculated EDFs suggest that Class AB PAs operating at low frequency (10 GHz) are more robust to hot carrier effects than when operating under DC or high frequency RF (up to 40 GHz). Also, operation under Class A yields higher EDFs than Class AB indicating lower reliability. This study is followed in chapter 5 by the proposal of a novel π-Shaped gate contact for GaN HEMTs which effectively reduces the hot electron generation while preserving device performance. Finally, in chapter 6 the electro-thermal characterization of GaN-on-Si HEMTs is performed by means of an expanded CMC framework, where charge and heat transport are self-consistently coupled. After the electro-thermal model is validated to experimental data, the assessment of self-heating under lateral scaling is considered.

MESFETs are used in high frequency applications and are typically made from GaAs. Dr. Trevor Thornton designed a silicon-on-insulator MESFET \u2014 a cheaper alternative with competitive capabilities. This paper concerns the characterization and modeling of this device to exhibit its marketability as a CMOS integrated transistor. Overviews of the MESFET's history and DLTS (deep level transient spectroscopy) are offered.

The Metal Semiconductor Field Effect Transistor (MESFET) has high potential to enter analog and RF applications due to their high breakdown voltage and switching frequency characteristics. These MESFET devices could allow for high voltage analog circuits to be integrated with low voltage digital circuits on a single chip in an extremely cost effective way. Higher integration leads to electronics with increased functionality and a smaller finished product. The MESFETs are designed in-house by the research group led by Dr. Trevor Thornton. The layouts are then sent to multi-project wafer (MPW) integrated circuit foundry companies, such as the Metal Oxide Semiconductor Implementation Service (MOSIS) to be fabricated. Once returned, the electrical characteristics of the devices are measured. The MESFET has been implemented in various applications by the research group, including the low dropout linear regulator (LDO) and RF power amplifier. An advantage of the MESFET is that it can function in extreme environments such as space, allowing for complex electrical systems to continue functioning properly where traditional transistors would fail.