Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-µm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation.

As wireless communication enters smartphone era, more complicated communication technologies are being used to transmit higher data rate. Power amplifier (PA) has to work in back-off region, while this inevitably reduces battery life for cellphones. Various techniques have been reported to increase PA efficiency, such as envelope elimination and restoration (EER) and envelope tracking (ET). However, state of the art ET supply modulators failed to address high efficiency, high slew rate, and accurate tracking concurrently.

In this dissertation, a linear-switch mode hybrid ET supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class-AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 V/µs to 93.4 V/µs and -87 V/µs to -152.5 V/µs respectively, dc gain from 45 dB to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power added efficiency (PAE) of 42.3% at 26.2 dBm for a 10 MHz 7.24 dB peak-to-average power ratio (PAPR) LTE signal and improves PAE by 8% at 6 dB back off from 26.2 dBm power amplifier (PA) output power with respect to fixed supply. With a 10 MHz 7.24 dB PAPR QPSK LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of -37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2 dBm PA output power, while with a 10 MHz 8.15 dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of -35.6 dBc and EVM of 6% at 26 dBm PA output power without digital pre-distortion (DPD). The proposed supply modulator core circuit occupies 1.1 mm2 die area, and is fabricated in a 0.18 µm CMOS technology.

Having the proper biomechanical and neuromuscular kinematics while performing an athletic motion is essential for athletes. Deviations from proper form in execution of the kinetic chain of an athletic movement may result in suboptimal performance and oftentimes an elevated likelihood of injury. The solutions currently available to athletes to account for digression from proper form are limited to sight and feel analysis of movement by the athletes and coaches and basic medical and athletic analysis equipment that is unsuitable for real-time analysis, the rigor and speed of dynamic athletic motions, and in-field use. The solution proposed herein is one of an in-shoe force measurement and foot positioning system designed to measure the ground reaction force generated by and alignment of an athlete's feet during an athletic motion. Research into various sports has found that the feet play a foundational role in proper execution of the kinetic chain, wherein the alignment, positioning, force generation, and timing of the feet may dictate proper execution of subsequent segments in the kinetic chain. The goal of the present design is to provide athletes with a solution to allow for real-time kinematic analysis of athletic motions using an in-shoe force measurement and foot positioning system. An understanding into the compensatory effect of foot misalignment, mismatched timing, and under or overcompensated ground reaction force generation by the feet on ensuing segments of the kinetic chain in conjunction with the present design can allow for athletes to measure and determine their degree of accuracy in form execution and to predict potential injuries resulting from deviations in form. Our design of an athletic shoe comprising an in-shoe force measurement system provides a dynamic solution to sports-related injuries presently unavailable to athletes.

A Multi-input single inductor dual-output Boost based architecture for Multi-junction PV energy harvesting source is presented. The system works in Discontinuous Conduction Mode to achieve the independent input regulation for multi-junction PV source. A dual-output path is implemented to regulate the output at 3V as well as store the extra energy at light load condition. The dual-loop based sliding-mode MPPT for multi-junction PV is proposed to speed up the system response time for prompt irradiation change as well as maximize MPPT efficiency. The whole system achieves peak efficiency of 83% and MPPT efficiency of 95%. The whole system is designed, simulated in Cadence and implemented in PCB platform.

This thesis presents a power harvesting system combining energy from sub-cells of

multi-junction photovoltaic (MJ-PV) cells. A dual-input, inductor time-sharing boost

converter in continuous conduction mode (CCM) is proposed. A hysteresis inductor current

regulation in designed to reduce cross regulation caused by inductor-sharing in CCM. A

modified hill-climbing algorithm is implemented to achieve maximum power point

tracking (MPPT). A dual-path architecture is implemented to provide a regulated 1.8V

output. A proposed lossless current sensor monitors transient inductor current and a time-based power monitor is proposed to monitor PV power. The PV input provides power of

65mW. Measured results show that the peak efficiency achieved is around 85%. The

power switches and control circuits are implemented in standard 0.18um CMOS process.

Traditional wireless communication systems operate in duplexed modes i.e. using time division duplexing or frequency division duplexing. These methods can respectively emulate full duplex mode operation or realize full duplex mode operation with decreased spectral efficiency. This thesis presents a novel method of achieving full duplex operation by actively cancelling out the transmitted signal in pseudo-real time. With appropriate hardware, the algorithms and techniques used in this work can be implemented in real time without any knowledge of the channel or any training sequence. Convergence times of down to 1 ms can be achieved which is adequate for the coherence bandwidths associated with an indoor environment. By utilizing adaptive cancellation, additional overhead for re-calibrating the system in other open-loop methods is not needed.

The modern era of consumer electronics is dominated by compact, portable, affordable smartphones and wearable computing devices. Power management integrated circuits (PMICs) play a crucial role in on-chip power management, extending battery life and efficiency of integrated analog, radio-frequency (RF), and mixed-signal cores. Low-dropout (LDO) regulators are commonly used to provide clean supply for low voltage integrated circuits, where point-of-load regulation is important. In System-On-Chip (SoC) applications, digital circuits can change their mode of operation regularly at a very high speed, imposing various load transient conditions for the regulator. These quick changes of load create a glitch in LDO output voltage, which hamper performance of the digital circuits unfavorably. For an LDO designer, minimizing output voltage variation and speeding up voltage glitch settling is an important task.

The presented research introduces two fully integrated LDO voltage regulators for SoC applications. N-type Metal-Oxide-Semiconductor (NMOS) power transistor based operation achieves high bandwidth owing to the source follower configuration of the regulation loop. A low input impedance and high output impedance error amplifier ensures wide regulation loop bandwidth and high gain. Current-reused dynamic biasing technique has been employed to increase slew-rate at the gate of power transistor during full-load variations, by a factor of two. Three design variations for a 1-1.8 V, 50 mA NMOS LDO voltage regulator have been implemented in a 180 nm Mixed-mode/RF process. The whole LDO core consumes 0.130 mA of nominal quiescent ground current at 50 mA load and occupies 0.21 mm x mm. LDO has a dropout voltage of 200 mV and is able to recover in 30 ns from a 65 mV of undershoot for 0-50 pF of on-chip load capacitance.

The photovoltaic systems used to convert solar energy to electricity pose a multitude of design and implementation challenges, including energy conversion efficiency, partial shading effects, and power converter efficiency. Using power converters for Distributed Maximum Power Point Tracking (DMPPT) is a well-known architecture to significantly reduce power loss associated with mismatched panels. Sub-panel-level DMPPT is shown to have up to 14.5% more annual energy yield than panel-level DMPPT, and requires an efficient medium power converter.

This research aims at implementing a highly efficient power management system at sub-panel level with focus on system cost and form-factor. Smaller form-factor motivates increased converter switching frequencies to significantly reduce the size of converter passives and substantially improve transient performance. But, currently available power MOSFETs put a constraint on the highest possible switching frequency due to increased switching losses. The solution is Gallium Nitride based power devices, which deliver figure of merit (FOM) performance at least an order of magnitude higher than existing silicon MOSFETs. Low power loss, high power density, low cost and small die sizes are few of the qualities that make e-GaN superior to its Si counterpart. With careful design, e-GaN can enable a 20-30% improvement in power stage efficiency compared to converters using Si MOSFETs.

The main objective of this research is to develop a highly integrated, high efficiency, 20MHz, hybrid GaN-CMOS DC-DC MPPT converter for a 12V/5A sub-panel. Hard and soft switching boost converter topologies are investigated within this research, and an innovative CMOS gate drive technique for efficiently driving an e-GaN power stage is presented in this work. The converter controller also employs a fast converging analog MPPT control technique.

A single solar cell provides close to 0.5 V output at its maximum power point, which is very

low for any electronic circuit to operate. To get rid of this problem, traditionally multiple

solar cells are connected in series to get higher voltage. The disadvantage of this approach

is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can

result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)

at single solar cell level is the most efficient way to extract power from solar cell.

Power Management IC (MPIC) used to extract power from single solar cell, needs to

start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area

overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an

auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.

The auxiliary supply powers up a MPPT converter followed by a regulated converter. At

the start up both the converters operate at 100 kHz clock with 80% duty cycle and system

output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up

circuit is turned off and the supply voltage for both the converters is derived from the system

output itself. In steady-state condition the system output is regulated to 3.0 V.

A fully integrated analog MPPT technique is proposed to extract maximum power from

the solar cell. This technique does not require Analog to Digital Converter (ADC) and

Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed

MPPT techniques includes a switch capacitor based power sensor which senses current of

boost converter without using any sense resistor. A complete system is designed which

starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.

As residential photovoltaic (PV) systems become more and more common and widespread, their system architectures are being developed to maximize power extraction while keeping the cost of associated electronics to a minimum. An architecture that has become popular in recent years is the "DC optimizer" architecture, wherein one DC-DC converter is connected to the output of each PV module. The DC optimizer architecture has the advantage of performing maximum power-point tracking (MPPT) at the module level, without the high cost of using an inverter on each module (the "microinverter" architecture). This work details the design of a proposed DC optimizer. The design incorporates a series-input parallel-output topology to implement MPPT at the sub-module level. This topology has some advantages over the more common series-output DC optimizer, including relaxed requirements for the system's inverter. An autonomous control scheme is proposed for the series-connected converters, so that no external control signals are needed for the system to operate, other than sunlight. The DC optimizer in this work is designed with an emphasis on efficiency, and to that end it uses GaN FETs and an active clamp technique to reduce switching and conduction losses. As with any parallel-output converter, phase interleaving is essential to minimize output RMS current losses. This work proposes a novel phase-locked loop (PLL) technique to achieve interleaving among the series-input converters.