The world has seen a revolution in cellular communication with the advent of 5G (fifth-generation), which enables gigabits per second data speed with low latency, massive capacity, and increased availability. These modern wireless systems improve spectrum efficiency by employing advanced modulation techniques, but result in large peak-to-average power ratios (PAPR) of the transmitted signals that degrades the efficiency of the radio-frequency power amplifiers (PAs) in the power back-off (PBO) region. Envelope tracking (ET), which is a dynamic supply control technology to realize high efficiency PAs, is a promising approach for designing transmitters for the future. Conventional voltage regulators, such as linear regulators and switching regulators, fail to simultaneously offer high speed, high efficiency, and improved linearity. Hybrid supply modulators (HSM) that combine a linear and switching regulator emerge as promising solutions to achieve an optimized tradeoff between different design parameters. Over the years, considerable development and research efforts in industry and academia have been spent on maximizing HSM performance, and a majority of the most recently developed modulators are implemented in CMOS technology and mainly targeted for handset applications. In this dissertation, the main requirements for modern HSM designs are categorized and analyzed in detail. Next, techniques to improve HSM performance are discussed. The available device technologies for HSM and PA implementations are also delineated, and implementation challenges of an integrated ET-PA system are summarized. Finally, a Current-Mode with Dynamic Hysteresis HSM is proposed, designed, and implemented. With the proposed technique, the HSM is able to track LTE signals up to 100 MHz bandwidth. Switching at a peak frequency of 40 MHz, the design is able to track a 1 Vpp sinusoidal signal with high fidelity, has an output voltage ripple around 54 mV, and achieves a peak static and dynamic efficiency of 92.2% and 82.29%, respectively, at the maximum output. The HSM is capable of delivering a maximum output power of 425 mW and occupies a small die area of 1.6mm2. Overall, the proposed HSM promises competitive performance compared to state-of-the-art works.

Power management integrated circuit (PMIC) design is a key module in almost all electronics around us such as Phones, Tablets, Computers, Laptop, Electric vehicles, etc. The on-chip loads such as microprocessors cores, memories, Analog/RF, etc. requires multiple supply voltage domains. Providing these supply voltages from off-chip voltage regulators will increase the overall system cost and limits the performance due to the board and package parasitics. Therefore, an on-chip fully integrated voltage regulator (FIVR) is required.

The dissertation presents a topology for a fully integrated power stage in a DC-DC buck converter achieving a high-power density and a time-domain hysteresis based highly integrated buck converter. A multi-phase time-domain comparator is proposed in this work for implementing the hysteresis control, thereby achieving a process scaling friendly highly digital design. A higher-order LC notch filter along with a flying capacitor which couples the input and output voltage ripple is implemented. The power stage operates at 500 MHz and can deliver a maximum power of 1.0 W and load current of 1.67 A, while occupying 1.21 mm2 active die area. Thus achieving a power density of 0.867 W/mm2 and current density of 1.377 A/mm2. The peak efficiency obtained is 71% at 780 mA of load current. The power stage with the additional off-chip LC is utilized to design a highly integrated current mode hysteretic buck converter operating at 180 MHz. It achieves 20 ns of settling and 2-5 ns of rise/fall time for reference tracking.

The second part of the dissertation discusses an integrated low voltage switched-capacitor based power sensor, to measure the output power of a DC-DC boost converter. This approach results in a lower complexity, area, power consumption, and a lower component count for the overall PV MPPT system. Designed in a 180 nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes 0.748 mW of power.

A single solar cell provides close to 0.5 V output at its maximum power point, which is very

low for any electronic circuit to operate. To get rid of this problem, traditionally multiple

solar cells are connected in series to get higher voltage. The disadvantage of this approach

is the efficiency loss for partial shading or mismatch. Even as low as 6-7% of shading can

result in more than 90% power loss. Therefore, Maximum Power Point Tracking (MPPT)

at single solar cell level is the most efficient way to extract power from solar cell.

Power Management IC (MPIC) used to extract power from single solar cell, needs to

start at 0.3 V input. MPPT circuitry should be implemented with minimal power and area

overhead. To start the PMIC at 0.3 V, a switch capacitor charge pump is utilized as an

auxiliary start up circuit for generating a regulated 1.8 V auxiliary supply from 0.3 V input.

The auxiliary supply powers up a MPPT converter followed by a regulated converter. At

the start up both the converters operate at 100 kHz clock with 80% duty cycle and system

output voltage starts rising. When the system output crosses 2.7 V, the auxiliary start up

circuit is turned off and the supply voltage for both the converters is derived from the system

output itself. In steady-state condition the system output is regulated to 3.0 V.

A fully integrated analog MPPT technique is proposed to extract maximum power from

the solar cell. This technique does not require Analog to Digital Converter (ADC) and

Digital Signal Processor (DSP), thus reduces area and power overhead. The proposed

MPPT techniques includes a switch capacitor based power sensor which senses current of

boost converter without using any sense resistor. A complete system is designed which

starts from 0.3 V solar cell voltage and provides regulated 3.0 V system output.