From Fully Depleted Silicon-on-insulator Towards Graphene-based Spintronic Applications

In the last few decades, extensive research efforts have been focused on scaling down silicon-based complementary metal-oxide semiconductor (CMOS) technology to enable the continuation of Moore’s law. State-of-art CMOS includes fully depleted silicon-on-insulator (FDSOI) field-effect-transistors (FETs) with ultra-thin silicon channels (6 nm), as well as other three-dimensional (3D) device architectures like Fin-FETs, nanosheet FETs, etc. Significant research efforts have characterized these technologies towards various applications, and at different conditions including a wide range of temperatures from room temperature (300 K) down to cryogenic temperatures. Theoretical efforts have studied ultrascaled devices using Landauer theory to further understand their transport properties and predict their performance in the quasi-ballistic regime.Further scaling of CMOS devices requires the introduction of new semiconducting channel materials, as now established by the research community. Here, two-dimensional (2D) semiconductors have emerged as a promising candidate to replace silicon for next-generation ultrascaled CMOS devices. These emerging 2D semiconductors also have applications beyond CMOS, for example in novel memory, neuromorphic, and spintronic devices. Graphene is a promising candidate for spintronic devices due to its outstanding spin transport properties as evidenced by numerous studies in non-local lateral spin valve (LSV) geometries. The essential components of graphene-based LSV, such as graphene FETs, metal-graphene contacts, and tunneling barriers, were individually investigated as part of this doctoral dissertation. In this work, several contributions were made to these CMOS and beyond CMOS technologies. This includes comprehensive characterization and modeling of FDSOI nanoscale FETs from room temperature down to cryogenic temperatures. Using Landauer theory for nanoscale transistors, FDSOI devices were analyzed and modeled under quasi-ballistic operation. This was extended towards a virtual-source modeling approach that accounts for temperature-dependent quasi-ballistic transport and back-gate biasing effects. Additionally, graphene devices with ultrathin high-k gate dielectrics were investigated towards FETs, non-volatile memory, and spintronic devices. New contributions were made relating to charge trapping effects and their impact on graphene device electrostatics (Dirac voltage shifts) and transport properties (impact on mobility and conductivity). This work also studied contact resistance and tunneling effects using transfer length method (TLM) graphene FET structures and magnetic tunneling junction (MTJ) towards graphene-based LSV.