In-field characterization of photovoltaics is crucial to understanding performance and degradation mechanisms, subsequently improving overall reliability and lifespans. Current outdoor characterization is often limited by logistical difficulties, variable weather, and requirements to measure during peak production hours. It becomes a challenge to find a characterization technique that is affordable with a low impact on system performance while still providing useful device parameters. For added complexity, this characterization technique must have the ability to scale for implementation in large powerplant applications. This dissertation addresses some of the challenges of outdoor characterization by expanding the knowledge of a well-known indoor technique referred to as Suns-VOC. Suns-VOC provides a pseudo current-voltage curve that is free of any effects from series resistance. Device parameters can be extracted from this pseudo I-V curve, allowing for subsequent degradation analysis. This work introduces how to use Suns-VOC outdoors while normalizing results based on the different effects of environmental conditions. This technique is validated on single-cells, modules, and small arrays with accuracies capable of measuring yearly degradation. An adaptation to Suns-VOC, referred to as Suns-Voltage-Resistor (Suns-VR), is also introduced to complement the results from Suns-VOC. This work can potentially be used to provide a diagnostic tool for outdoor characterization in various applications, including residential, commercial, and industrial PV systems.

Metallization of solar cells is a critical process step in the manufacturing of silicon photovoltaics (PV) as it plays a large role in device performance and production cost. Improvements in device performance linked to metallization and reduction in material usage and processing costs will continue to drive next-generation silicon PV technology. Chapter 1 introduces the context for the contributions of this thesis by providing background information on silicon PV cell technology, solar cell device physics and characterization, and metallization performance for common silicon cell structures. Chapter 2 presents a thermal model that links sub-bandgap reflectance, an important metric at the rear metal interface, to outdoor module operating temperature. Chapter 3 implements this model experimentally with aluminum back-surface field (Al-BSF), passivated emitter and rear contact (PERC), and passivated emitter rear totally diffused (PERT) mini-modules, where the PERT cells were modified to include an optimized sub-bandgap reflector stack. The dedicated optical layer was a porous low-refractive index silica nanoparticle film and was deposited between the dielectric passivation and full area metallization. This created an appreciable boost in sub-bandgap reflectance over the PERC and Al-BSF cells, which directly lead to cooler operating temperature of the fielded module. Chapter 4 investigates low-temperature Ag metallization approaches to SiO2/polysilicon passivating contacts (TOPCon architecture). The low-temperature Ag sintering process does not damage TOPCon passivation for structures with 40-nm-thick poly-Si but shows higher contact resistivity than sputtered references. This disparity is investigated and the impact of Ag diffusion processes, microstructure changes, ambient gases, and interfacial chemical reactions are evaluated. Chapter 5 investigates sputtered Al metallization to silicon heterojunction contacts of both polarities. This In-free and Ag-free metallization process can achieve low contact resistivity and no passivation loss when annealed between 150-180 °C. The passivation degradation at higher temperatures was studied with high-resolution microscopy and elemental mapping, where the interdiffusion processes were identified. Lastly, Chapter 6 summarizes the contribution of this work.

This work explores the application and optimization of laser patterning of dielectrics on textured crystalline silicon for improving the performance of industrial silicon solar cells. Current direct laser patterning processes introduce defects to the surface of the solar cell as a result of the film transparency and the intensity variation of the laser induced by the textured surface. As a means of overcoming these challenges, a co-deposited protective masking film was developed that is directly patterned with laser light at greatly depreciated light intensities that allows for selective chemical etching of the underlying dielectric films without incurring substantial defects to the surface of the device. Initial defects produced by the process are carefully evaluated with electron microscopy techniques and their mechanism for generation is identified and compensated. Further, an analysis of the opening fraction within the laser spot is evaluated –the area of removed film within the laser spot divided by the area of the laser spot– and residue produced by the laser process within the contact opening is studied. Once identified, this non-damaging laser process is a promising alternative to the standard screen print and fire process currently used by industry for metallization of silicon solar cells. Smaller contacts may be made with the laser process that are as of yet unattainable with screen printing, allowing for a decrease in shading losses. Additionally, the use of patterning allows for silver-free metallization and improved conductivity in the contacts, thereby decreasing parasitic losses in the device.

Silicon photovoltaics (PV) is approaching its theoretical efficiency limit as a single-junction technology. To break this limit and further lower the PV-generated levelized cost of electricity, it is necessary to engineer a silicon-based “tandem” technology in which a solar cell of another material is stacked on top of silicon to make more efficient use of the full solar spectrum.

This dissertation understands and develops four aspects of silicon-based tandem PV technology. First, a new “spectral efficiency” concept is proposed to understand how tandem cells should be designed and to identify the best tandem partners for silicon cells. Using spectral efficiency, a top-cell-design guide is constructed for silicon-based tandems that sets efficiency targets for top cells with various bandgaps to achieve targeted tandem efficiencies.

Second, silicon heterojunction solar cells are tuned to the near-infrared spectrum to enable world-record perovskite/silicon tandems both in two- and four-terminal configurations. In particular, for the 23.6%-efficient two-terminal tandem, a single-side textured silicon bottom cell is fabricated with a low-refractive-index silicon nanoparticle layer as a rear reflector. This design boosts the current density to 18.5 mA/cm2; this value exceeds that of any other silicon bottom cell and matches that of the top cell.

Third, “PVMirrors” are proposed as a novel tandem architecture to integrate silicon cells with various top cells. A strength of the design is that the PVMirror collects diffuse light as a concentrating technology. With this concept, a gallium-arsenide/silicon PVMirror tandem is demonstrated with an outdoor efficiency of 29.6%, with respect to the global irradiance.

Finally, a simple and versatile analytical model is constructed to evaluate the cost competitiveness of an arbitrary tandem against its sub-cell alternatives. It indicates that tandems will become increasingly attractive in the market, as the ratio of sub-cell module cost to area-related balance-of-system cost—the key metric that will determine the market success or failure of tandems—is decreasing.

As an evolution of silicon technology, silicon-based tandems are the future of PV. They will allow more people to have access to clean energy at ultra-low cost. This thesis defines both the technological and economic landscape of silicon-based tandems, and makes important contributions to this tandem future.

Silicon solar cells with heterojunction carrier collectors based on a-Si/c-Si heterojunction (SHJ) have a potential to overcome the limitations of the conventional diffused junction solar cells and become the next industry standard manufacturing technology of solar cells. A brand feature of SHJ technology is ultrapassivated surfaces with already demonstrated 750 mV open circuit voltages (Voc) and 24.7% efficiency on large area solar cell. Despite very good results achieved in research and development, large volume manufacturing of high efficiency SHJ cells remains a fundamental challenge. The main objectives of this work were to develop a SHJ solar cell fabrication flow using industry compatible tools and processes in a pilot production environment, study the interactions between the used fabrication steps, identify the minimum set of optimization parameters and characterization techniques needed to achieve 20% baseline efficiency, and analyze the losses of power in fabricated SHJ cells by numerical and analytical modeling. This manuscript presents a detailed description of a SHJ solar cell fabrication flow developed at ASU Solar Power Laboratory (SPL) which allows large area solar cells with >750 mV Voc. SHJ cells on 135 um thick 153 cm2 area wafers with 19.5% efficiency were fabricated. Passivation quality of (i)a-Si:H film, bulk conductivity of doped a-Si films, bulk conductivity of ITO, transmission of ITO and the thickness of all films were identified as the minimum set of optimization parameters necessary to set up a baseline high efficiency SHJ fabrication flow. The preparation of randomly textured wafers to minimize the concentration of surface impurities and to avoid epitaxial growth of a-Si films was found to be a key challenge in achieving a repeatable and uniform passivation. This work resolved this issue by using a multi-step cleaning process based on sequential oxidation in nitric/acetic acids, Piranha and RCA-b solutions. The developed process allowed state of the art surface passivation with perfect repeatability and negligible reflectance losses. Two additional studies demonstrated 750 mV local Voc on 50 micron thick SHJ solar cell and < 1 cm/s effective surface recombination velocity on n-type wafers passivated by a-Si/SiO2/SiNx stack.