In order to ensure higher penetration of photovoltaics in the energy market and have an immediate impact in addressing the challenges of energy crisis and climate change, this thesis research focusses on improving the efficiency of the diffused junction silicon solar cells of an already existing line with established processes. Thus, the baseline processes are first made stable and demonstrated as a pilot line at the Solar Power Lab at ASU, to be used as a backbone on which further improvements could be made. Of the several factors that affect the solar cell efficiency, improvement of short circuit current by reduction of the shading losses is chosen to achieve the improvement.

The shading losses are reduced by lowering the finger width of the solar cell .This reduction of the front metal coverage causes an increase in the series resistance, thereby adversely affecting the fill factor and hence efficiency. To overcome this problem, double printing method is explored to be used for front grid metallization. Before its implementation, it is important to accurately understand the effect of reducing the finger width on the series resistance. Hence, series resistance models are modified from the existing generic model and developed to capture the effects of screen-printing. To have minimum power loss in the solar cell, finger spacing is optimized for the front grid design with each of the finger widths chosen, which are narrower than the baseline finger width. A commercial software package called Griddler is used to predict the results of the model developed to capture effects of screen-printing.

The process for double printing with accurate alignment for finger width down to 50um is developed. After designing the screens for optimized front grid, solar cells are fabricated using both single printing and double printing methods and an improvement of efficiency from 17.2% to 17.8%, with peak efficiency of 18% is demonstrated.

The aim of this thesis research is the development of thin silicon heterojunction solar cells with high open circuit voltage (Voc). Heterojunction solar cells are higher in efficiency than diffused junction c-Si solar cells, and they are less vulnerable to light degradation. Furthermore, the low temperature processing of heterojunction cells favour a decrease in production costs and improve cell performance at the same time. Since about 30 % of the module cost is a result of substrate cost, thin solar cells are of economic advantage than their thicker counterparts. This lead to the research for development of thin heterojunction solar cells. For high cell efficiencies and performance, it is important for cells to have a high operating voltage and Voc. Development of heterojunction cells with high Voc required a stable and repeatable baseline process on which further improvements could be made. Therefore a baseline process for heterojunction solar cells was developed and demonstrated as a pilot line at the Solar Power Lab at ASU. All the processes involved in fabrication of cells with the baseline process were optimized to have a stable and repeatable process. The cells produced with the baseline process were 19-20% efficient. The baseline process was further used as a backbone to improve and develop thin cells with even higher Voc. The process recipe was optimized with an aim to explore the limits of Voc that could be achieved with this structure on a much thinner substrate than used for the baseline process. A record Voc greater than 760mV was recorded at SPL using Suns-Voc tester on a 50 microns thick heterojunction cell without metallization. Furthermore, Voc of 754.2 mV was measured on a 50 microns thick cell with metallization by National Renewable Energy Laboratory (NREL), which is a record for Voc for heterojunction cells with metallization. High Voc corresponds to high cell efficiency and therefore, higher module voltage and power with using the same number of cells as compared to other c-Si solar cells.

Silicon (Si) solar cells are the dominant technology used in the Photovoltaics industry. Field-effect passivation by means of electrostatic charges stored in an overlying insulator on a silicon solar cell has been proven to be a significantly efficient way to reduce effective surface recombination velocity and increase minority carrier lifetime. Silicon nitride (SiNx) films have been extensively used as passivation layers. The capability to store charges makes SiNx a promising material for excellent feild effect passivation. In this work, symmetrical Si/SiO2/SiNx stacks are developed to study the effect of charges in SiNx films. SiO2 films work as barrier layers. Corona charging technique showed the ability to inject charges into the SiNx films in a short time. Minority carrier lifetimes of the Czochralski (CZ) Si wafers increased significantly after either positive or negative charging. A fast and contactless method to characterize the charged overlying insulators on Si wafer through lifetime measurements is proposed and studied in this work, to overcome the drawbacks of capacitance-voltage (CV) measurements such as time consuming, induction of contanmination and hysteresis effect, etc. Analytical simulations showed behaviors of inverse lifetime (Auger corrected) vs. minority carrier density curves depend on insulator charge densities (Nf). From the curve behavior, the Si surface condition and region of Nf can be estimated. When the silicon surface is at high strong inversion or high accumulation, insulator charge density (Nf) or surface recombination velocity parameters (Sn0 and Sp0) can be determined from the slope of inverse lifetime curves, if the other variable is known. If Sn0 and Sp0 are unknown, Nf values of different samples can be compared as long as all have similar Sn0 and Sp0 values. Using the saturation current density (J0) and intercept fit extracted from the lifetime measurement, the bulk lifetime can be calculated. Therefore, this method is feasible and promising for charged insulator characterization.

Silicon solar cells with heterojunction carrier collectors based on a-Si/c-Si heterojunction (SHJ) have a potential to overcome the limitations of the conventional diffused junction solar cells and become the next industry standard manufacturing technology of solar cells. A brand feature of SHJ technology is ultrapassivated surfaces with already demonstrated 750 mV open circuit voltages (Voc) and 24.7% efficiency on large area solar cell. Despite very good results achieved in research and development, large volume manufacturing of high efficiency SHJ cells remains a fundamental challenge. The main objectives of this work were to develop a SHJ solar cell fabrication flow using industry compatible tools and processes in a pilot production environment, study the interactions between the used fabrication steps, identify the minimum set of optimization parameters and characterization techniques needed to achieve 20% baseline efficiency, and analyze the losses of power in fabricated SHJ cells by numerical and analytical modeling. This manuscript presents a detailed description of a SHJ solar cell fabrication flow developed at ASU Solar Power Laboratory (SPL) which allows large area solar cells with >750 mV Voc. SHJ cells on 135 um thick 153 cm2 area wafers with 19.5% efficiency were fabricated. Passivation quality of (i)a-Si:H film, bulk conductivity of doped a-Si films, bulk conductivity of ITO, transmission of ITO and the thickness of all films were identified as the minimum set of optimization parameters necessary to set up a baseline high efficiency SHJ fabrication flow. The preparation of randomly textured wafers to minimize the concentration of surface impurities and to avoid epitaxial growth of a-Si films was found to be a key challenge in achieving a repeatable and uniform passivation. This work resolved this issue by using a multi-step cleaning process based on sequential oxidation in nitric/acetic acids, Piranha and RCA-b solutions. The developed process allowed state of the art surface passivation with perfect repeatability and negligible reflectance losses. Two additional studies demonstrated 750 mV local Voc on 50 micron thick SHJ solar cell and < 1 cm/s effective surface recombination velocity on n-type wafers passivated by a-Si/SiO2/SiNx stack.

Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.