The Physics and Chemistry of Surfaces and Interfaces conference has maintained a focus on the interfacial and surface properties of materials since its initiation in 1974. The conference continues to be a major force in this field, bringing together scientists from a variety of disciplines to focus upon the science of interfaces and surfaces. Here, a historical view of the development of the conference and a discussion of some of the themes that have been focal points for many years are presented.

ABSTRACT An Ensemble Monte Carlo (EMC) computer code has been developed to simulate, semi-classically, spin-dependent electron transport in quasi two-dimensional (2D) III-V semiconductors. The code accounts for both three-dimensional (3D) and quasi-2D transport, utilizing either 3D or 2D scattering mechanisms, as appropriate. Phonon, alloy, interface roughness, and impurity scattering mechanisms are included, accounting for the Pauli Exclusion Principle via a rejection algorithm. The 2D carrier states are calculated via a self-consistent 1D Schrödinger-3D-Poisson solution in which the charge distribution of the 2D carriers in the quantization direction is taken as the spatial distribution of the squared envelope functions within the Hartree approximation. The wavefunctions, subband energies, and 2D scattering rates are updated periodically by solving a series of 1D Schrödinger wave equations (SWE) over the real-space domain of the device at fixed time intervals. The electrostatic potential is updated by periodically solving the 3D Poisson equation. Spin-polarized transport is modeled via a spin density-matrix formalism that accounts for D'yakanov-Perel (DP) scattering. Also, the code allows for the easy inclusion of additional scattering mechanisms and structural modifications to devices. As an application of the simulator, the current voltage characteristics of an InGaAs/InAlAs HEMT are simulated, corresponding to nanoscale III-V HEMTs currently being fabricated by Intel Corporation. The comparative effects of various scattering parameters, material properties and structural attributes are investigated and compared with experiments where reasonable agreement is obtained. The spatial evolution of spin-polarized carriers in prototypical Spin Field Effect Transistor (SpinFET) devices is then simulated. Studies of the spin coherence times in quasi-2D structures is first investigated and compared to experimental results. It is found that the simulated spin coherence times for GaAs structures are in reasonable agreement with experiment. The SpinFET structure studied is a scaled-down version of the InGaAs/InAlAs HEMT discussed in this work, in which spin-polarized carriers are injected at the source, and the coherence length is studied as a function of gate voltage via the Rashba effect.

Semiconductor nanowires are featured by their unique one-dimensional structure which makes them promising for small scale electronic and photonic device applications. Among them, III-V material nanowires are particularly outstanding due to their good electronic properties. In bulk, these materials reveal electron mobility much higher than conventional silicon based devices, for example at room temperature, InAs field effect transistor (FET) has electron mobility of 40,000 cm2/Vs more than 10 times of Si FET. This makes such materials promising for high speed nanowire FETs. With small bandgap, such as 0.354 eV for InAs and 1.52 eV for GaAs, it does not need high voltage to turn on such devices which leads to low power consumption devices. Another feature of direct bandgap allows their applications of optoelectronic devices such as avalanche photodiodes. However, there are challenges to face up. Due to their large surface to volume ratio, nanowire devices typically are strongly affected by the surface states. Although nanowires can be grown into single crystal structure, people observe crystal defects along the wires which can significantly affect the performance of devices. In this work, FETs made of two types of III-V nanowire, GaAs and InAs, are demonstrated. These nanowires are grown by catalyst-free MOCVD growth method. Vertically nanowires are transferred onto patterned substrates for coordinate calibration. Then electrodes are defined by e-beam lithography followed by deposition of contact metals. Prior to metal deposition, however, the substrates are dipped in ammonium hydroxide solution to remove native oxide layer formed on nanowire surface. Current vs. source-drain voltage with different gate bias are measured at room temperature. GaAs nanowire FETs show photo response while InAs nanowire FETs do not show that. Surface passivation is performed on GaAs FETs by using ammonium surfide solution. The best results on current increase is observed with around 20-30 minutes chemical treatment time. Gate response measurements are performed at room temperature, from which field effect mobility as high as 1490 cm2/Vs is extracted for InAs FETs. One major contributor for this is stacking faults defect existing along nanowires. For InAs FETs, thermal excitations observed from temperature dependent results which leads us to investigate potential barriers.

Graphene, a one atomic thick planar sheet of carbon atoms, has a zero gap band structure with a linear dispersion relation. This unique property makes graphene a favorite for physicists and engineers, who are trying to understand the mechanism of charge transport in graphene and using it as channel material for field effect transistor (FET) beyond silicon. Therefore, an in-depth exploring of these electrical properties of graphene is urgent, which is the purpose of this dissertation. In this dissertation, the charge transport and quantum capacitance of graphene were studied. Firstly, the transport properties of back-gated graphene transistor covering by high dielectric medium were systematically studied. The gate efficiency increased by up to two orders of magnitude in the presence of a high top dielectric medium, but the mobility did not change significantly. The results strongly suggested that the previously reported top dielectric medium-induced charge transport properties of graphene FETs were possibly due to the increase of gate capacitance, rather than enhancement of carrier mobility. Secondly, a direct measurement of quantum capacitance of graphene was performed. The quantum capacitance displayed a non-zero minimum at the Dirac point and a linear increase on both sides of the minimum with relatively small slopes. The findings - which were not predicted by theory for ideal graphene - suggested that scattering from charged impurities also influences the quantum capacitance. The capacitances in aqueous solutions at different ionic concentrations were also measured, which strongly suggested that the longstanding puzzle about the interfacial capacitance in carbon-based electrodes had a quantum origin. Finally, the transport and quantum capacitance of epitaxial graphene were studied simultaneously, the quantum capacitance of epitaxial graphene was extracted, which was similar to that of exfoliated graphene near the Dirac Point, but exhibited a large sub-linear behavior at high carrier density. The self-consistent theory was found to provide a reasonable description of the transport data of the epitaxial graphene device, but a more complete theory was needed to explain both the transport and quantum capacitance data.