Integrating analog circuits with the most advanced digitally-tuned processes increases the defect rates and the risk of in-field wear out. Coupled with the reduced accessibility arising from this level of integration, increasing defect rates necessitate systematic approaches to analog testing. Structural built-in self-test (BIST) for analog circuits can reduce test development complexity. Proposing a robust and low-cost structural BIST method for analog circuits. The proposed method relies on perturbing the analog circuit at an injection point and observing the result at an observation point as a digitally measurable time delay. Injection can be achieved via simple ON/OFF keying while the observation can be achieved by a self-referencing comparator. Multiple injection points can be selected at low cost (single transistor) while the observation circuit can be shared across many injection points and different circuit blocks.

The world has seen a revolution in cellular communication with the advent of 5G (fifth-generation), which enables gigabits per second data speed with low latency, massive capacity, and increased availability. These modern wireless systems improve spectrum efficiency by employing advanced modulation techniques, but result in large peak-to-average power ratios (PAPR) of the transmitted signals that degrades the efficiency of the radio-frequency power amplifiers (PAs) in the power back-off (PBO) region. Envelope tracking (ET), which is a dynamic supply control technology to realize high efficiency PAs, is a promising approach for designing transmitters for the future. Conventional voltage regulators, such as linear regulators and switching regulators, fail to simultaneously offer high speed, high efficiency, and improved linearity. Hybrid supply modulators (HSM) that combine a linear and switching regulator emerge as promising solutions to achieve an optimized tradeoff between different design parameters. Over the years, considerable development and research efforts in industry and academia have been spent on maximizing HSM performance, and a majority of the most recently developed modulators are implemented in CMOS technology and mainly targeted for handset applications. In this dissertation, the main requirements for modern HSM designs are categorized and analyzed in detail. Next, techniques to improve HSM performance are discussed. The available device technologies for HSM and PA implementations are also delineated, and implementation challenges of an integrated ET-PA system are summarized. Finally, a Current-Mode with Dynamic Hysteresis HSM is proposed, designed, and implemented. With the proposed technique, the HSM is able to track LTE signals up to 100 MHz bandwidth. Switching at a peak frequency of 40 MHz, the design is able to track a 1 Vpp sinusoidal signal with high fidelity, has an output voltage ripple around 54 mV, and achieves a peak static and dynamic efficiency of 92.2% and 82.29%, respectively, at the maximum output. The HSM is capable of delivering a maximum output power of 425 mW and occupies a small die area of 1.6mm2. Overall, the proposed HSM promises competitive performance compared to state-of-the-art works.

In this dissertation, enhanced coherent detection of terahertz (THz) radiation is presented for Silicon integrated circuits (ICs). In general THz receivers implemented in silicon technologies face a challenge due to the high noise figure (NF) of the low noise amplifier (LNA) and low conversion gain of the radio frequency (RF) mixers. Moreover, issues with implementing local oscillators (LOs) further compound these challenges, including power driving mixes, distribution networks, and overall power consumption, particularly for large-scale arrays. To address these inherent obstacles, two notable cases of enhancing THz receiver performance are presented. In the Sideband Separation Receiver (SSR) for space-borne applications is introduced. Implemented in SiGe BiCMOS technology this broadband SSR boasts a high Image Rejection Ratio (IRR) exceeding 20 dB across 220 – 320 GHz. Employing a modified Weaver architecture, optimized for simultaneous spectral line observation, it utilizes an I/Q double down-conversion, pushing the technological boundaries of silicon and enabling large-scale focal plane array (FPA) deployment in space. Notably, the use of a sub-harmonic down-conversion mixer (SHM) significantly reduces LO power generation challenges, enhancing scalability while maintaining minimal NF. In the 4x4 FPA active THz imager, a dual-polarized patch antenna operating at 420 GHz utilizes orthogonal polarization for RF and LO signals, coupled with a coherent homodyne power detector. Realized in 0.13µm SiGe HBT technology, the power detector is co-designing with the antenna to ensure minimal crosstalk and achieving -30dB cross-polarization isolation. Illumination of the LO enhances power detector performance without on-chip routing complexities, enabling scalability to 1K pixel THz imagers. Each pixel achieves a Noise-Equivalent Power (NEP) of 1 pW/√Hz at 420 GHz, and integration with a readout and digital filter ensures high dynamic range. Furthermore, this study explores radiation hardening techniques to mitigate single-event effects (SEEs) in high-frequency receivers operating in space. Leveraging a W-band receiver in 90 nm SiGe BiCMOS technology, matching considerations and diverse modes of operation are employed to reduce SEE susceptibility. Transient current pulse modeling, validated through TCAD simulations, demonstrates the effectiveness of proposed techniques in substantially mitigating SETs within the proposed radiation-hardened-by-design (RHBD) receiver front-end.

Recent advancements in communication standards, such as 5G demand transmitter hardware to support high data rates with high energy efficiency. With the revolution of communication standards, modulation schemes have become more complex and require high peak-to-average (PAPR) signals. In wireless transceiver hardware, the power amplifier (PA) consumes most of the transceiver’s DC power and is typically the bottleneck for transmitter linearity. Therefore, the transmitter’s performance directly depends on the PA. To support high PAPR signals, the PA must operate efficiently at its saturated and backoff output power. Maintaining high efficiency at both peak and backoff output power is challenging. One effective technique for addressing this problem is load modulation. Some of the prominent load-modulated PA architectures are outphasing PAs, load-modulated balanced amplifiers (LMBA), envelope elimination and restoration (EER), envelope tracking (ET), Doherty power amplifiers (DPA), and polar transmitters. Amongst them, the DPA is the most popular for infrastructure applications due to its simpler architecture compared to other techniques and linearizability with digital pre-distortion (DPD). Another crucial characteristic of progressing communication standards is wide signal bandwidths. High-efficiency power amplifiers like class J/F/F-1 and load-modulated PAs like the DPA exhibit narrowband performance because the amplifiers require precise output impedance terminations. Therefore, it is equally essential to develop adaptable PA solutions to process radio frequency (RF) signals with wide bandwidths. To support modern and future cellular infrastructure, RF PAs need to be innovated to increase the backoff power efficiency by two times or more and support ten times or more wider bandwidths than current state-of-the-art PAs. This work presents five RF PA analyses and implementations to support future wireless communications transmitter hardware. Chapter 2 presents an optimized output-matching network analysis and design to achieve extended output power backoff of the DPA. Chapters 3 and 4 unveil two bandwidth enhancement techniques for the DPA while maintaining extended output power backoff. Chapter 5 exhibits a dual-band hybrid mode PA design targeted for wideband applications. Chapter 6 presents a built-in self-test circuit integrated into a PA for output impedance monitoring. This can alleviate the PA performance degradation due to the variation in the PA's output load over frequency, process, and aging. All RF PAs in this dissertation are implemented using Gallium Nitride (GaN)-based high electron mobility transistors (HEMT), and the realized designs validate the proposed PAs' theories/architectures.

This work presents two balanced power amplifier (PA) architectures, one at X-band and the other at K-band. The presented balanced PAs are designed for use in small satellite and cube satellite applications.The presented X-band PA employs wideband hybrid couplers to split input power to two commercial off-the-shelf (COTS) Gallium Nitride (GaN) monolithic microwave integrated circuit (MMIC) PAs and combine their output powers. The presented X-band balanced PA manufactured on a Rogers 4003C substrate yields increased small signal gain and saturated output power under continuous wave (CW) operation compared to the single MMIC PA used in the design under pulsed operation. The presented PA operates from 7.5 GHz to 11.5 GHz, has a maximum small signal gain of 36.3 dB, a maximum saturated power out of 40.0 dBm, and a maximum power added efficiency (PAE) of 38%. Both a Wilkinson and a Gysel splitter and combiner are designed for use at K-band and their performance is compared. The presented K-band balanced PA uses Gysel power dividers and combiners with a GaN MMIC PA that is soon to be released in production.

Impedance is one of the fundamental properties of electrical components, materials, and waves. Therefore, impedance measurement and monitoring have a wide range of applications. The multi-port technique is a natural candidate for impedance measurement and monitoring due to its low overhead and ease of implementation for Built-in Self-Test (BIST) applications. The multi-port technique can measure complex reflection coefficients, thus impedance, by using scalar measurements provided by the power detectors. These power detectors are strategically placed on different points (ports) of a passive network to produce unique solution. Impedance measurement and monitoring is readily deployed on mobile phone radio-frequency (RF) front ends, and are combined with antenna tuners to boost the signal reception capabilities of phones. These sensors also can be used in self-healing circuits to improve their yield and performance under process, voltage, and temperature variations. Even though, this work is preliminary interested in low-overhead impedance measurement for RF circuit applications, the proposed methods can be used in a wide variety of metrology applications where impedance measurements are already used. Some examples of these applications include determining material properties, plasma generation, and moisture detection. Additionally, multi-port applications extend beyond the impedance measurement. There are applications where multi-ports are used as receivers for communication systems, RADARs, and remote sensing applications. The multi-port technique generally requires a careful design of the testing structure to produce a unique solution from power detector measurements. It also requires the use of nonlinear solvers during calibration, and depending on calibration procedure, measurement. The use of nonlinear solvers generates issues for convergence, computational complexity, and resources needed for carrying out calibrations and measurements in a timely manner. In this work, using periodic structures, a structure where a circuit block repeats itself, for multi-port measurements is proposed. The periodic structures introduce a new constraint that simplifies the multi-port theory and leads to an explicit calibration and measurement procedure. Unlike the existing calibration procedures which require at least five loads and various constraints on the load for explicit solution, the proposed method can use three loads for calibration. Multi-ports built with periodic structures will always produce a unique measurement result. This leads to increased bandwidth of operation and simplifies design procedure. The efficacy of the method demonstrated in two embodiments. In the first embodiment, a multi-port is directly embedded into a matching network to measure impedance of the load. In the second embodiment, periodic structures are used to compare two loads without requiring any calibration.

Handheld devices and personal laptops are becoming compact and complex every year with a demand to have higher power density, efficiency, and fast transient response. DC-DC boost converters are used in display and haptic drivers where the output voltage needs to be boosted higher than input voltage. The load transient response and unity gain bandwidth (UGB) of DC-DC boost converters are restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. The fast feedback (FFB) path is designed to achieve low output voltage change and fast settling time with the same UGB when compared to the conventional peak current mode control (CPCM). In the proposed PFFC method, the closed loop output impedance (ZOCL) is improved by reducing the DC value and by increasing the bandwidth of ZOCL as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for VOUT=5V, VIN=2.5V-4.4V and ILOAD=10mA-1A operating at a frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by ~2.6X and the undershoot reduces by 62% to 12μs and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/μs. The PFFC approach improves the settling time by 12X to 26us and reduces the overshoot by 56% to 56mV when compared to CPCM for 1A to 10mA load step at 2A/μs. The converter achieves a peak efficiency of 95.2% at 0.5W output power with VIN=4.4V and load regulation of 9mV/A at VIN=2.5V. The line transient response at VOUT=5V, ILOAD=700mA for VIN=3V ↔ 4V which is repeated at 280μs time period is 235mV and 245mV for CPCM and PFFC respectively.

Modern-day automobiles are becoming more connected and reliant on wireless connectivity. Thus, automotive electronics can be both a cause of and highly sensitive to electromagnetic interference (EMI), and the consequences of failure can be fatal. Technology advancements in engineering have brought several features into the automotive field but at the expense of electromagnetic compatibility issues. Automotive EMC problems are the result of the emissions from electronic assemblies inside a vehicle and the susceptibility of the electronics when exposed to external EMI sources. In both cases, automotive EMC problems can cause unintended changes in the automotive system operation. Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state-of-the-art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this dissertation an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via the substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle, and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics.

The world has seen a revolution in cellular communication with the advent of 5G, which enables gigabits per second data speed with low latency, massive capacity, and increased availability. Complex modulated signals are used in these moderncommunication systems to achieve high spectral efficiency, and these signals exhibit high peak to average power ratios (PAPR). Design of cellular infrastructure hardware to support these complex signals therefore becomes challenging, as the transmitter’s radio frequency power amplifier (RF PA) needs to remain highly efficient at both peak and backed off power conditions. Additionally, these PAs should exhibit high linearity and support continually increasing bandwidths. Many advanced PA configurations exhibit high efficiency for processing legacy communications signals. Some of the most popular architectures are Envelope Elimination and Restoration (EER), Envelope Tracking (ET), Linear Amplification using Non-linear Component (LINC), Doherty Power Amplifiers (DPA), and Polar Transmitters. Among these techniques, the DPA is the most widely used architecture for base-station applications because of its simple configuration and ability to be linearized using simple digital pre-distortion (DPD) algorithms. To support the cellular infrastructure needs of 5G and beyond, RF PAs, specifically DPA architectures, must be further enhanced to support broader bandwidths as well as smaller form-factors with higher levels of integration. The following four novel works are presented in this dissertation to support RF PA requirements for future cellular infrastructure: 1. A mathematical analysis to analyze the effects of non-linear parasitic capacitance (Cds) on the operation of continuous class-F (CCF) mode power amplifiers and identify their optimum operating range for high power and efficiency. 2. A methodology to incorporate a class-J harmonic trapping network inside the PA package by considering the effect of non-linear Cds, thus reducing the DPA footprint while achieving high RF performance. 3. A novel method of synthesizing the DPA’s output combining network (OCN) to realize an integrated two-stage integrated LDMOS asymmetric DPA. 4. A novel extended back-off efficiency range DPA architecture that engineers the mutual interaction between combining load and peaking off-state impedance. The theory and architecture are verified through a GaN-based DPA design.