Handheld devices and personal laptops are becoming compact and complex every year with a demand to have higher power density, efficiency, and fast transient response. DC-DC boost converters are used in display and haptic drivers where the output voltage needs to be boosted higher than input voltage. The load transient response and unity gain bandwidth (UGB) of DC-DC boost converters are restricted by the presence of a right half plane zero (RHPZ). In this paper, a control scheme termed peak current fast feedback control (PFFC) is proposed to improve the load transient response without the need for additional power switches or passive components. The fast feedback (FFB) path is designed to achieve low output voltage change and fast settling time with the same UGB when compared to the conventional peak current mode control (CPCM). In the proposed PFFC method, the closed loop output impedance (ZOCL) is improved by reducing the DC value and by increasing the bandwidth of ZOCL as compared to conventional peak current mode control (CPCM), thus improving the steady state and transient performance. The fast feedback (FFB) path is implemented within the error amplifier (EA) with an increase of only 2% in the active area as compared to CPCM. The boost converter is designed for VOUT=5V, VIN=2.5V-4.4V and ILOAD=10mA-1A operating at a frequency of 2MHz. Measurement results show that with PFFC enabled, the settling time reduces by ~2.6X and the undershoot reduces by 62% to 12μs and 41mV respectively when compared to CPCM for 10mA to 1A load step at 2A/μs. The PFFC approach improves the settling time by 12X to 26us and reduces the overshoot by 56% to 56mV when compared to CPCM for 1A to 10mA load step at 2A/μs. The converter achieves a peak efficiency of 95.2% at 0.5W output power with VIN=4.4V and load regulation of 9mV/A at VIN=2.5V. The line transient response at VOUT=5V, ILOAD=700mA for VIN=3V ↔ 4V which is repeated at 280μs time period is 235mV and 245mV for CPCM and PFFC respectively.

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby

accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum

load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.