Machine learning advancements have led to increasingly complex algorithms, resulting in significant energy consumption due to heightened memory-transfer requirements and inefficient vector matrix multiplication (VMM). To address this issue, many have proposed ReRAM analog in-memory computing (AIMC) as a solution. AIMC enhances the time-energy efficiency of VMM operations beyond conventional VMM digital hardware, such as a tensor processing unit (TPU), while substantially reducing memory-transfer demands through in-memory computing. As AIMC gains prominence as a solution, it becomes crucial to optimize ReRAM and analog crossbar architecture characteristics. This thesis introduces an application-specific integrated circuit (ASIC) tailored forcharacterizing ReRAM within a crossbar array architecture and discusses the interfacing techniques employed. It discusses ReRAM forming and programming techniques and showcases chip’s ability to utilize the write-verify programming method to write image pixels on a conductance heat map. Additionally, this thesis assesses the ASIC’s capability to characterize different aspects of ReRAM, including drift and noise characteristics. The research employs the chip to extract ReRAM data and models it within a crossbar array simulator, enabling its application in the classification of the CIFAR-10 dataset.

Metal-Oxide-Semiconductor (MOS) is essential to modern VLSI devices. In the past decades, a wealth of literature has been created to understand the impact of the radiation-induced charges on the devices, i.e., the creation of electron-hole pairs in the oxide layer which is the most sensitive part of MOS structure to the radiation effect. In this work, both MOS and MNOS devices were fabricated at ASU NanoFab to study the total ionizing dose effect using capacitance-voltage (C-V) electrical characterization by observing the direction and amounts of the shift in C-V curves and electron holography observation to directly image the charge buildup at the irradiated oxide film of the oxide-only MOS device.C-V measurements revealed the C-V curves shifted to the left after irradiation (with a positive bias applied) because of the net positive charges trapped at the oxide layer for the oxide-only sample. On the other hand, for nitride/oxide samples with positive biased during irradiation, the C-V curve shifted to the right due to the net negative charges trapped at the oxide layer. It was also observed that the C-V curve has less shift in voltage for MNOS than MOS devices after irradiation due to the less charge buildup after irradiation. Off-axis electron holography was performed to map the charge distribution across the MOSCAP sample. Compared with both pre-and post-irradiated samples, a larger potential drop at the Si/SiO2 was noticed in post-irradiation samples, which indicates the presence of greater amounts of positive charges that buildup the Si/SiO2 interface after the TID exposure. TCAD modeling was used to extract the density of charges accumulated near the SiO2/Si and SiO2/ Metal interface by matching the simulation results to the potential data from holography. The increase of near-interface positive charges in post-irradiated samples is consistent with the C-V results.

My honors thesis took the form of a creative project. My final deliverables are my research presentation (pdf attachment) and solar powered electric scooter (image attachment). The goal of my project was to fix a second-hand electric scooter and create a solar-powered charger for its battery. The research portion of my creative project focused on exploring the circuit elements in a solar charging schematic and their relationships to power output. First, I explored methods of maximizing power output of the basic solar charging schematic. To find the maximum power output based on different settings of photocurrent (sunlight), I wrote a MATLAB code to calculate maximum power based on its derivative with respect to voltage set equal to zero. Finding this maximum power point in MATLAB allowed me to find its corresponding current and voltage output to produce that exact power. With these max current and voltage values, I was able to solve for an ideal resistor value to set in series with the solar panel in order to achieve these values. In doing so, I designed a maximum power point tracker (MPPT). This became an essential component in my charger’s final design. Next, I explored the microcircuit level of a solar panel schematic. In order to do so, I had to break my single diode model into several diodes in series, resulting in the overall solar panel voltage drop (aka the voltage rating of the solar panel) being divided N times. To find what this N value for a given solar panel is, I performed a lab experiment using a small solar panel and a floodlight to gather the panel’s turn on current and open circuit voltage. These two values helped me find the solar panel’s N value after linearizing the lab data. Now, with a much deeper understanding of solar charging circuitry, I was able to move forward with the design and implementation phase. The design and implementation portion of my creative project included the physical assembly of the solar-powered scooter. First, I analyzed the efficiency differences between having an AC coupled vs. DC coupled system. Due to the added complexity of AC conversions, I deemed it unnecessary to use an inverter in the charger. The charging schematic I designed only called for a charge controller and MPPT, both parts that could easily DC couple the system. Keeping the system in DC from solar panel to battery was definitely the most efficient method, so DC coupling was my final selection. Next, I calculated the required current and voltage output of my charger to meet the specs of the battery and the requirements I set for my project. Finally, I designed a solar array based on these ratings. The final design includes one 30 W panel in parallel with two series-connected 5W panels. The two series panels are affixed on the scooter neck for a built in charge design so that the scooter can be charged anywhere (outside while not in use). The big panel can be connected using a parallel branch in the charging cord that I spliced for added current if charging is set up in a stationary setting (by a window at home). The final design serves the need for sustainable micro mobility in a daily 50% depletion use case kept above 20% charged at all times.

The Deep Neural Network (DNN) is one type of a neuromorphic computing approach that has gained substantial interest today. To achieve continuous improvement in accuracy, the depth, and the size of the deep neural network needs to significantly increase. As the scale of the neural network increases, it poses a severe challenge to its hardware implementation with conventional Computer Processing Unit (CPU) and Graphic Processing Unit (GPU) from the perspective of power, computation, and memory. To address this challenge, domain specific specialized digital neural network accelerators based on Field Programmable Gate Array (FPGAs) and Application Specific Integrated Circuits (ASICs) have been developed. However, limitations still exist in terms of on-chip memory capacity, and off-chip memory access. As an alternative, Resistive Random Access Memories (RRAMs), have been proposed to store weights on chip with higher density and enabling fast analog computation with low power consumption. Conductive Bridge Random Access Memories (CBRAMs) is a subset of RRAMs, whose conductance states is defined by the existence and modulation of a conductive metal filament. Ag-Chalcogenide based Conductive Bridge RAM (CBRAM) devices have demonstrated multiple resistive states making them potential candidates for use as analog synapses in neuromorphic hardware. In this work the use of Ag-Ge30Se70 device as an analog synaptic device has been explored. Ag-Ge30Se70 CBRAM crossbar array was fabricated. The fabricated crossbar devices were subjected to different pulsing schemes and conductance linearity response was analyzed. An improved linear response of the devices from a non-linearity factor of 6.65 to 1 for potentiation and -2.25 to -0.95 for depression with non-identical pulse application is observed. The effect of improved linearity was quantified by simulating the devices in an artificial neural network. Simulations for area, latency, and power consumption of the CBRAM device in a neural accelerator was conducted. Further, the changes caused by Total Ionizing Dose (TID) in the conductance of the analog response of Ag-Ge30Se70 Conductive Bridge Random Access Memory (CBRAM)-based synapses are studied. The effect of irradiation was further analyzed by simulating the devices in an artificial neural network. Material characterization was performed to understand the change in conductance observed due to TID.

Recently, the implementation of neuromorphic accelerator hardware has gradually changed from traditional Von Neumann architectures to non-Von Neumann architectures due to the “memory wall” and “power wall”. Near-memory computing (NMC) and In- memory computing (IMC) are two common types of non-Von Neumann approaches. NMC can help reduce data movements, yet it cannot fully address the challenge of improving computational efficiency as the neural network size grows. IMC has been proposed as a superior alternative. This architecture performs computation inside the memory array using stackable synaptic devices to improve the latency and the energy efficiency of neural network accelerators. Both volatile and non-volatile computational memory devices can achieve IMC. Fully complementary metal-oxide semiconductor (CMOS) in-memory computing cells can be realized by adding additional transistors in standard static random access memory (SRAM) bit-cell. The SRAM-based designs investigated in this dissertation perform bit-wise logical operation to obtain XNOR-and-accumulate computation (XAC) for deep neural networks (DNNs). Hybrid in-memory computing architectures combine CMOS with embedded non-volatile memory (eNVM). Resistive random access memory (RRAM) is one class of eNVM ideally suited for hybrid IMC. In a neural network, RRAM with programmable multi-level resistance/conductance states can naturally emulate weight transitions in the synaptic elements of neural networks. In this dissertation, the operation and effects of ionizing radiation effects on both fully CMOS and hybrid IMCs are investigated. The fully CMOS architectures preform SRAM-based XAC computations. The hybrid architectures use multi-state RRAM synapse with CMOS neurons to perform multiply-and-accumulate computation (MAC). In the SRAM XAC array, an 8×8 XNOR IMC array is modeled with flipped-well enhanced-gate super low threshold voltage (EGSLVT) metal-oxide semiconductor field-effect transistors (MOSFETs) from the GlobalFoundries 22nm fully depleted silicon on insulator (FDSOI) process. The impact of total ionizing dose (TID) on the XAC synaptic array is analyzed by using radiation-aware models to mimic TID-induced voltage shifts in MOSFETs. In multi- state RRAM MAC array, 4-state conductance has been programmed in hafnium-oxide (HfOx) RRAM 1-transistor-1-resistor (1T1R) array. The impact of total ionizing dose on the multi-state behavior of HfOx RRAM is evaluated by irradiating a 64kb 1T1R array with 90nm CMOS peripheral circuitry under Co-60 γ-ray irradiation.

Bipolar commercial-off-the-shelf (COTS) circuits are increasingly used in spacemissions due to the low cost per part. In space environments these devices are exposed to ionizing radiation that degrades their performance. Testing to evaluate the performance of these devices is a costly and lengthy process. As such methods that can help predict a COTS part’s performance help alleviate these downsides. A modeling software for predicting total ionizing dose (TID), enhanced low dose rate sensitivity (ELDRS), and hydrogen gas on bipolar parts is introduced and expanded upon. The model is then developed in several key ways that expand it’s features and usability in this field. A physics based methodology of simulating interface traps (NIT) to expand the previously experimental only database is detailed. This new methodology is also compared to experimental data and used to establish a link between hydrogen concentration in the oxide and packaged hydrogen gas. Links are established between Technology Computer Aided Design (TCAD), circuit simulation, and experimental data. These links are then used to establish a better foundation for the model. New methodologies are added to the modeling software so that it is possible to simulate transient based characteristics like slew rate.

Proton beam therapy has been proven to be effective for cancer treatment. Protons allow for complete energy deposition to occur inside patients, rendering this a superior treatment compared to other types of radiotherapy based on photons or electrons. This same characteristic makes quality assurance critical driving the need for detectors capable of direct beam positioning and fluence measurement. This work showcases a flexible and scalable data acquisition system for a multi-channel and segmented readout parallel plate ionization chamber instrument for proton beam fluence and positioning detection. Utilizing readily available, modern, off-the-shelf hardware components, including an FPGA with an embedded CPU in the same package, a data acquisition system for the detector was designed. The undemanding detector signal bandwidth allows the absence of ASICs and their associated costs and lead times in the system. The data acquisition system is showcased experimentally for a 96-readout channel detector demonstrating sub millisecond beam characteristics and beam reconstruction. The system demonstrated scalability up to 1064-readout channels, the limiting factor being FPGA I/O availability as well as amplification and sampling power consumption.