As integrated technologies are scaling down, there is an increasing trend in the

process,voltage and temperature (PVT) variations of highly integrated RF systems.

Accounting for these variations during the design phase requires tremendous amount

of time for prediction of RF performance and optimizing it accordingly. Thus, there

is an increasing gap between the need to relax the RF performance requirements at

the design phase for rapid development and the need to provide high performance

and low cost RF circuits that function with PVT variations. No matter how care-

fully designed, RF integrated circuits (ICs) manufactured with advanced technology

nodes necessitate lengthy post-production calibration and test cycles with expensive

RF test instruments. Hence design-for-test (DFT) is proposed for low-cost and fast

measurement of performance parameters during both post-production and in-eld op-

eration. For example, built-in self-test (BIST) is a DFT solution for low-cost on-chip

measurement of RF performance parameters. In this dissertation, three aspects of

automated test and calibration, including DFT mathematical model, BIST hardware

and built-in calibration are covered for RF front-end blocks.

First, the theoretical foundation of a post-production test of RF integrated phased

array antennas is proposed by developing the mathematical model to measure gain

and phase mismatches between antenna elements without any electrical contact. The

proposed technique is fast, cost-efficient and uses near-field measurement of radiated

power from antennas hence, it requires single test setup, it has easy implementation

and it is short in time which makes it viable for industrialized high volume integrated

IC production test.

Second, a BIST model intended for the characterization of I/Q offset, gain and

phase mismatch of IQ transmitters without relying on external equipment is intro-

duced. The proposed BIST method is based on on-chip amplitude measurement as

in prior works however,here the variations in the BIST circuit do not affect the target

parameter estimation accuracy since measurements are designed to be relative. The

BIST circuit is implemented in 130nm technology and can be used for post-production

and in-field calibration.

Third, a programmable low noise amplifier (LNA) is proposed which is adaptable

to different application scenarios depending on the specification requirements. Its

performance is optimized with regards to required specifications e.g. distance, power

consumption, BER, data rate, etc.The statistical modeling is used to capture the

correlations among measured performance parameters and calibration modes for fast

adaptation. Machine learning technique is used to capture these non-linear correlations and build the probability distribution of a target parameter based on measurement results of the correlated parameters. The proposed concept is demonstrated by

embedding built-in tuning knobs in LNA design in 130nm technology. The tuning

knobs are carefully designed to provide independent combinations of important per-

formance parameters such as gain and linearity. Minimum number of switches are

used to provide the desired tuning range without a need for an external analog input.

Point of Load (PoL) converters are important components to the power distribution system in computer power supplies as well as automotive, space, nuclear, and medical electronics. These converters often require high output current capability, low form factor, and high conversion ratios (step-down) without sacrificing converter efficiency. This work presents hybrid silicon/gallium nitride (CMOS/GaN) power converter architectures as a solution for high-current, small form-factor PoL converters. The presented topologies use discrete GaN power devices and CMOS integrated drivers and controller loop. The presented power converters operate in the tens of MHz range to reduce the form factor by reducing the size of the off-chip passive inductor and capacitor. Higher conversion ratio is achieved through a fast control loop and the use of GaN power devices that exhibit low parasitic gate capacitance and minimize pulse swallowing.

This work compares three discrete buck power converter architectures: single-stage, multi-phase with 2 phases, and stacked-interleaved, using components-off-the-shelf (COTS). Each of the implemented power converters achieves over 80% peak efficiency with switching speeds up-to 10MHz for high conversion ratio from 24V input to 5V output and maximum load current of 10A. The performance of the three architectures is compared in open loop and closed loop configurations with respect to efficiency, output voltage ripple, and power stage form factor.

Additionally, this work presents an integrated CMOS gate driver solution in CMOS 0.35um technology. The CMOS integrated circuit (IC) includes the gate driver and the closed loop controller for directly driving a single-stage GaN architecture. The designed IC efficiently drives the GaN devices up to 20MHz switching speeds. The presented controller technique uses voltage mode control with an innovative cascode driver architecture to allow a 3.3V CMOS devices to effectively drive GaN devices that require 5V gate signal swing. Furthermore, the designed power converter is expected to operate under 400MRad of total dose, thus enabling its use in high-radiation environments for the large hadron collider at CERN and nuclear facilities.

Current technology does not allow for the full amount of power produced by solar arrays (PV) on spacecraft to be utilized. The arrays are designed with non-reconfigurable architectures and sent on fifteen to twenty year long missions. They cannot be changed once they are in space, so the arrays are designed for the end of life. Throughout their lifetime, solar arrays can degrade in power producing capabilities anywhere from 20% to 50%. Because there is such a drastic difference in the beginning and end of life power production, and because they cannot be reconfigured, a new design has been found necessary in order to increase power production. Reconfiguration allows the solar arrays to achieve maximum power producing capabilities at both the beginning and end of their lives. With the potential to increase power production by 50%, the reconfiguration design consists of a switching network to be able to utilize any combination of cells. The design for reconfiguration must meet the power requirements of the solar array. This thesis will explore different designs for reconfiguration, as well as possible switches for implementation. It will also review other methods to increase power production, as well as discuss future work in this field.

Performance failure due to aging is an increasing concern for RF circuits. While most aging studies are focused on the concept of mean-time-to-failure, for analog circuits, aging results in continuous degradation in performance before it causes catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is not just determined by aging at the device level, but also by the slack in the specifications, process variations, and the stress conditions on the devices. In this dissertation, firstly, a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices at design-time (pre-silicon) is presented. An algorithm to determine reliability hotspots in the circuit is proposed and design-time optimization methods to enhance the lifetime by making the most likely to fail circuit components more reliable is performed. RF circuits are used as test cases to demonstrate that the lifetime can be enhanced using the proposed design-time technique with low area and no performance impact. Secondly, in-field monitoring and recovering technique for the performance of aged RF circuits is discussed. The proposed in-field technique is based on two phases: During the design time, degradation profiles of the aged circuit are obtained through simulations. From these profiles, hotspot identification of aged RF circuits are conducted and the circuit variable that is easy to measure but highly correlated to the performance of the primary circuit is determined for a monitoring purpose. After deployment, an on-chip DC monitor is periodically activated and its results are used to monitor, and if necessary, recover the circuit performances degraded by aging mechanisms. It is also necessary to co-design the monitoring and recovery mechanism along with the primary circuit for minimal performance impact. A low noise amplifier (LNA) and LC-tank oscillators are fabricated for case studies to demonstrate that the lifetime can be enhanced using the proposed monitoring and recovery techniques in the field. Experimental results with fabricated LNA/oscillator chips show the performance degradation from the accelerated stress conditions and this loss can be recovered by the proposed mitigation scheme.

Complex electronic systems include multiple power domains and drastically varying dynamic power consumption patterns, requiring the use of multiple power conversion and regulation units. High frequency switching converters have been gaining prominence in the DC-DC converter market due to smaller solution size (higher power density) and higher efficiency. As the filter components become smaller in value and size, they are unfortunately also subject to higher process variations and worse degradation profiles jeopardizing stable operation of the power supply. This dissertation presents techniques to track changes in the dynamic loop characteristics of the DC-DC converters without disturbing the normal mode of operation. A digital pseudo-noise (PN) based stimulus is used to excite the DC-DC system at various circuit nodes to calculate the corresponding closed-loop impulse response. The test signal energy is spread over a wide bandwidth and the signal analysis is achieved by correlating the PN input sequence with the disturbed output generated, thereby

accumulating the desired behavior over time. A mixed-signal cross-correlation circuit is used to derive on-chip impulse responses, with smaller memory and lower computational requirement in comparison to a digital correlator approach. Model reference based parametric and non-parametric techniques are discussed to analyze the impulse response results in both time and frequency domain. The proposed techniques can extract open-loop phase margin and closed-loop unity-gain frequency within 5.2% and 4.1% error, respectively, for the load current range of 30-200mA. Converter parameters such as natural frequency (ω_n ), quality factor (Q), and center frequency (ω_c ) can be estimated within 3.6%, 4.7%, and 3.8% error respectively, over load inductance of 4.7-10.3µH, and filter capacitance of 200-400nF. A 5-MHz switching frequency, 5-8.125V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed built-in self-test (BIST) analysis. The converter output voltage range is 3.3-5V and the supported maximum

load current is 450mA. The peak efficiency of the converter is 87.93%. The proposed converter is fabricated on a 0.6µm 6-layer-metal Silicon-On-Insulator (SOI) technology with a die area of 9mm^2 . The area impact due to the system identification blocks including related I/O structures is 3.8% and they consume 530µA quiescent current during operation.

Testing and calibration constitute a significant part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. Developing a low-cost testing and calibration scheme applicable at the user side that ensures the continuous reliability and accuracy is a crucial need. The main purpose of testing is to eliminate defective devices and to verify the qualifications of a product is met. The calibration process for capacitive MEMS devices, for the most part, entails the determination of the mechanical sensitivity. In this work, a physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuity can extract the amplitude and phase response of the acceleration sensor's mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under the physical stimulus. Sensitivity characterization is performed using a low computation complexity multivariate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed-signal readout signal chain and the host processor core, without the need for computationally expensive Fast Fourier Transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18-µm CMOS technology. The sensor analog front-end and BIST circuitry are integrated with a three-axis, low-g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm2 with a total readout IC area of 1.0 mm2 and consumes 8.9 mW during self-test operation.

The purpose of the Simultaneous Transmit and Receive Antenna project is to design a test circuit that will allow us to use an antenna to both send out and receive a signal at the same time on the same frequency. The test circuit will generate DC voltage levels that we can use to solve for the gain and delay of the transmit interference, so we will then be able to cancel out the unwanted signal from the received signal. With a theoretically perfect setup, the transmitted signal will be able to be completely isolated from the received signal, leaving us with only what we want at the output. In practice, however, this is not the case. There are many variables that will affect the integrity of the DC output of the test signal. As the output voltage level deviates from its theoretical perfect measurement, the precision to which we are able to solve for the gain and delay values decreases. The focus of this study is to estimate the effect of using a digital measurement tool to measure the output of the test circuit. Assuming a voltmeter with 1 volt full range, simulations were run using measurements stored at different bit resolutions, from 8-bit storage up to 16-bit storage. Since the physical hardware for the Simultaneous Transmit and Receive test circuit is not currently available, these tests were performed with an edited version of the Matlab simulation created for the Senior Design project. The simulation was run 2000 times over each bit resolution to get a wide range of generated values, then the error from each run was analyzed to come to a conclusion on the effect of the digital measurement on the design. The results of these simulations as well as further details of the project and testing are described inside this document.

The capstone portion of this project was to use the established STaR antennas and add a Built in Self-Test system to ensure the quality of the signals being received. This part of the project required a MatLab simulation to be built, a layout created, and a PCB designed for fabrication. In theory, the test BiST unit will allow the gain and delay of the transmitted signal and then cancel out unneeded interference for the received signal. However, this design required multiple paths to maintain the same lengths to keep the signals in phase for comparison. The purpose of this thesis is to show the potential drop-offs of the quality of the signals from being out of phase due to the wires that should be similar, being off by a certain percentage. This project will calculate the theoretical delay of all wires being out of sync and then add this delay to the established MatLab simulation. This report will show the relationship between the error of the received variables and what the actual generated values. And, the last part of the document will demonstrate the simulation by creating a signal and comparing it to its received counterpart. The end result of the study showed that the percent error between what is seen and what is expected is near insignificant and, hence, not an issue with regards to the quality of the project.

The Built-In Self-Test for Simultaneous Transmit and Receive (BIST for STAR) will be able to solve the challenges of transmitting and receiving at the same time at the same frequency. One of the major components is the STAR antenna which transmits and receives along the same pathway. The main problem with doing both on the same path is that the transmit signal is usually much stronger in power compared to the received signal. The transmit signal has echoes and leakages that cause self-interference, preventing the received signal from being properly obtained. The solution developed in this project is the BIST component, which will help calculate the functional gain and phase offset of the interference signal and subtract it from the pathway so that the received signal remains. The functions of the proposed circuit board can be modeled in Matlab, where an emulation code generates a random, realistic functional gain and delay for the interference. From the generated values, the BIST for STAR was simulated to output what the measurements would be given the strength of the input signal and a controlled delay. The original Matlab code models an ideal environment directly recalculating the functional gain and phase from the given measurements in a second Matlab script. The actual product will not be ideal; a possible source of error to be considered is the effect of thermal noise. To observe the effect of noise on the BIST for STAR's performance, the Matlab code was expanded upon to include a component for thermal noise, and a method of analyzing the results of the board.

Accessibility to the internal nodes of an analog/mixed-signal circuit while testing is extremely difficult. Furthermore, with technology scaling, the effect of process variations becomes more pronounced which in turn effects the test time, test cost, and die yield. As devices become more unreliable, the probability of failure of a die increases, yield decreases affecting the quality of test and cost.Therefore, test time minimization and test cost reduction are important. Moreover, process variations can affect the performance of analog/mixed circuits. Therefore, the performance of a System On-Chip(SoC) which tends to integrate multiple band gap reference circuits (BGRs) is effected due to the wide variations caused in the behavior of the BGR as a result of increasing process variations. Calibration of the BGR is, thus, important in the test process so as to obtain accuracy in the measurement of the output voltage of BGR. Furthermore, as test time minimization and test cost reduction are important in a test process, Built-in Self Test (BIST) techniques have become more popular. To obtain accuracy in the measurement of the output voltage of BGR, a VCO-based zoom-in ADC architecture that was designed to calibrate the output of the BGR voltage which dictates the circuit performance. However, the zoom-voltages for the circuit are generated using a tester. As the number of such ADCs integrated on a SoC increase, the number of nodes to be accessed by the tester increase. Moreover, the capacitance of the probe affects the accuracy of the applied input voltages of the VCO-based ADC. Therefore, accessibility decreases with increase in scaling.Further, generating a wide range of inputs becomes burdensome for the tester. For all the above reasons, an on-chip DAC circuitry was proposed as a part of this thesis, to decrease the reliance on tester. The suggested DAC architecture is a simple resistor string whose resolution depends on the number of zoom-in voltages to be generated. This architecture has a linear and monotonic behavior which is very important as the VCO has a highly non-linear behavior. Thus, the voltages generated by the DAC should be accurate with minimum error so that the worst-case Integral Non-Linearity error (INL) is less than 1mV considering resistor mismatches over process variations. With the increase in the number of VCO-based ADCs on a chip, the test time savings increase exponentially. Thus, the introduction of an on-chip DAC circuitry offers various advantages like decreasing accessibility requirement during the test process, occupying less area, reducing test cost and most importantly, decreasing the reliance on tester.