Micro Electro Mechanical Systems (MEMS) based accelerometers are one of the most commonly used sensors out there. They are used in devices such as, airbags, smartphones, airplanes, and many more. Although they are very accurate, they degrade with time or get offset due to some damage. To fix this, they must be calibrated again using physical calibration technique, which is an expensive process to conduct. However, these sensors can also be calibrated infield by applying an on-chip electrical stimulus to the sensor. Electrical stimulus-based calibration could bring the cost of testing and calibration significantly down as compared to factory testing. In this thesis, simulations are presented to formulate a statistical prediction model based on an electrical stimulus. Results from two different approaches of electrical calibration have been discussed. A prediction model with a root mean square error of 1% has been presented in this work. Experiments were conducted on commercially available accelerometers to test the techniques used for simulations.

The manufacturing process for electronic systems involves many players, from chip/board design and fabrication to firmware design and installation.

In today's global supply chain, any of these steps are prone to interference from rogue players, creating a security risk.

Manufactured devices need to be verified to perform only their intended operations since it is not economically feasible to control the supply chain and use only trusted facilities.

It is becoming increasingly necessary to trust but verify the received devices both at production and in the field.

Unauthorized hardware or firmware modifications, known as Trojans,

can steal information, drain the battery, or damage battery-driven embedded systems and lightweight Internet of Things (IoT) devices.

Since Trojans may be triggered in the field at an unknown instance,

it is essential to detect their presence at run-time.

However, it isn't easy to run sophisticated detection algorithms on these devices

due to limited computational power and energy, and in some cases, lack of accessibility.

Since finding a trusted sample is infeasible in general, the proposed technique is based on self-referencing to remove any effect of environmental or device-to-device variations in the frequency domain.

In particular, the self-referencing is achieved by exploiting the band-limited nature of Trojan activity using signal detection theory.

When the device enters the test mode, a predefined test application is run on the device

repetitively for a known period. The periodicity ensures that the spectral electromagnetic power of the test application concentrates at known frequencies, leaving the remaining frequencies within the operating bandwidth at the noise level. Any deviations from the noise level for these unoccupied frequency locations indicate the presence of unknown (unauthorized) activity. Hence, the malicious activity can differentiate without using a golden reference or any knowledge of the Trojan activity attributes.

The proposed technique's effectiveness is demonstrated through experiments with collecting and processing side-channel signals, such as involuntarily electromagnetic emissions and power consumption, of a wearable electronics prototype and commercial system-on-chip under a variety of practical scenarios.

Developing countries suffer from various health challenges due to inaccessible medical diagnostic laboratories and lack of resources to establish new laboratories. One way to address these issues is to develop diagnostic systems that are suitable for the low-resource setting. In addition to this, applications requiring rapid analyses further motivates the development of portable, easy-to-use, and accurate Point of Care (POC) diagnostics. Lateral Flow Immunoassays (LFIAs) are among the most successful POC tests as they satisfy most of the ASSURED criteria. However, factors like reagent stability, reaction rates limit the performance and robustness of LFIAs. The fluid flow rate in LFIA significantly affect the factors mentioned above, and hence, it is desirable to maintain an optimal fluid velocity in porous media.

The main objective of this study is to build a statistical model that enables us to determine the optimal design parameters and ambient conditions for achieving a desired fluid velocity in porous media. This study mainly focuses on the effects of relative humidity and temperature on evaporation in porous media and the impact of geometry on fluid velocity in LFIAs. A set of finite element analyses were performed, and the obtained simulation results were then experimentally verified using Whatman filter paper with different geometry under varying ambient conditions. Design of experiments was conducted to estimate the significant factors affecting the fluid flow rate.

Literature suggests that liquid evaporation is one of the major factors that inhibit fluid penetration and capillary flow in lateral flow Immunoassays. The obtained results closely align with the existing literature and conclude that a desired fluid flow rate can be achieved by tuning the geometry of the porous media. The derived statistical model suggests that a dry and warm atmosphere is expected to inhibit the fluid flow rate the most and vice-versa.

Intracellular voltage recordings from single neurons in vitro and in vivo have been fundamental to our understanding of neuronal function. Conventional electrodes and associated positioning systems for intracellular recording in vivo are large and bulky, which has largely restricted their use to single-channel recording from anesthetized animals. Further, intracellular recordings are very cumbersome, requiring a high degree of skill not readily achieved in a typical laboratory. This dissertation presents a robotic, head-mountable, MEMS (Micro-Electro-Mechanical Systems) based intracellular recording system to overcome the above limitations associated with form-factor, scalability and highly skilled and tedious manual operations required for intracellular recordings. This system combines three distinct technologies: 1) novel microscale, polycrystalline silicon-based electrode for intracellular recording, 2) electrothermal microactuators for precise microscale navigation of the electrode and 3) closed-loop control algorithm for autonomous movement and positioning of electrode inside single neurons. First, two distinct designs of polysilicon-based microscale electrodes were fabricated and tested for intracellular recordings. In the first approach, tips of polysilicon microelectrodes were milled to nanoscale dimensions (<300 nm) using focused ion beam (FIB) to develop polysilicon nanoelectrodes. Polysilicon nanoelectrodes recorded >1.5 mV amplitude, positive-going action potentials and synaptic potentials from neurons in the abdominal ganglion of Aplysia Californica. In the second approach, polysilicon microelectrodes were integrated with miniaturized glass micropipettes filled with electrolyte to fabricate glass-polysilicon microelectrodes. These electrodes consistently recorded high fidelity intracellular potentials from neurons in the abdominal ganglion of Aplysia Californica (Resting Potentials < -35 mV, Action Potentials > 60 mV) as well as the rat motor cortex (Resting Potentials < -50 mV). Next, glass-polysilicon microelectrodes were coupled with microscale electrothermal actuators and controller for autonomous intracellular recordings from single neurons in the abdominal ganglion. Consistent resting potentials (< -35 mV) and action potentials (> 60 mV) were recorded after each successful penetration attempt with the controller and microactuated glass-polysilicon microelectrodes. The success rate of penetration and quality of recordings achieved using electrothermal microactuators were comparable to that of conventional positioning systems. Finally, the feasibility of this miniaturized system to obtain intracellular recordings from single neurons in the motor cortex of rats in vivo is also demonstrated. The MEMS-based system offers significant advantages: 1) reduction in overall size for potential use in behaving animals, 2) scalable approach to potentially realize multi-channel recordings and 3) a viable method to fully automate measurement of intracellular recordings.

Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations that can occur in the field lead to significant testing and validation challenges. For example, designers have to ensure that FHE devices continue to meet specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures developed for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. Then develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation.

Accessibility to the internal nodes of an analog/mixed-signal circuit while testing is extremely difficult. Furthermore, with technology scaling, the effect of process variations becomes more pronounced which in turn effects the test time, test cost, and die yield. As devices become more unreliable, the probability of failure of a die increases, yield decreases affecting the quality of test and cost.Therefore, test time minimization and test cost reduction are important. Moreover, process variations can affect the performance of analog/mixed circuits. Therefore, the performance of a System On-Chip(SoC) which tends to integrate multiple band gap reference circuits (BGRs) is effected due to the wide variations caused in the behavior of the BGR as a result of increasing process variations. Calibration of the BGR is, thus, important in the test process so as to obtain accuracy in the measurement of the output voltage of BGR. Furthermore, as test time minimization and test cost reduction are important in a test process, Built-in Self Test (BIST) techniques have become more popular. To obtain accuracy in the measurement of the output voltage of BGR, a VCO-based zoom-in ADC architecture that was designed to calibrate the output of the BGR voltage which dictates the circuit performance. However, the zoom-voltages for the circuit are generated using a tester. As the number of such ADCs integrated on a SoC increase, the number of nodes to be accessed by the tester increase. Moreover, the capacitance of the probe affects the accuracy of the applied input voltages of the VCO-based ADC. Therefore, accessibility decreases with increase in scaling.Further, generating a wide range of inputs becomes burdensome for the tester. For all the above reasons, an on-chip DAC circuitry was proposed as a part of this thesis, to decrease the reliance on tester. The suggested DAC architecture is a simple resistor string whose resolution depends on the number of zoom-in voltages to be generated. This architecture has a linear and monotonic behavior which is very important as the VCO has a highly non-linear behavior. Thus, the voltages generated by the DAC should be accurate with minimum error so that the worst-case Integral Non-Linearity error (INL) is less than 1mV considering resistor mismatches over process variations. With the increase in the number of VCO-based ADCs on a chip, the test time savings increase exponentially. Thus, the introduction of an on-chip DAC circuitry offers various advantages like decreasing accessibility requirement during the test process, occupying less area, reducing test cost and most importantly, decreasing the reliance on tester.

Alternative computation based on neural systems on a nanoscale device are of increasing interest because of the massive parallelism and scalability they provide. Neural based computation systems also offer defect finding and self healing capabilities. Traditional Von Neumann based architectures (which separate the memory and computation units) inherently suffer from the Von Neumann bottleneck whereby the processor is limited by the number of instructions it fetches. The clock driven based Von Neumann computer survived because of technology scaling. However as transistor scaling is slowly coming to an end with channel lengths becoming a few nanometers in length, processor speeds are beginning to saturate. This lead to the development of multi-core systems which process data in parallel, with each core being based on the Von Neumann architecture.

The human brain has always been a mystery to scientists. Modern day super computers are outperformed by the human brain in certain computations. The brain occupies far less space and consumes a fraction of the power a super computer does with certain processes such as pattern recognition. Neuromorphic computing aims to mimic biological neural systems on silicon to exploit the massive parallelism that neural systems offer. Neuromorphic systems are event driven systems rather than being clock driven. One of the issues faced by neuromorphic computing was the area occupied by these circuits. With recent developments in the field of nanotechnology, memristive devices on a nanoscale have been developed and show a promising solution. Memristor based synapses can be up to three times smaller than Complementary Metal Oxide Semiconductor (CMOS) based synapses.

In this thesis, the Programmable Metallization Cell (a memristive device) is used to prove a learning algorithm known as Spike Time Dependant Plasticity (STDP). This learning algorithm is an extension to Hebb’s learning rule in which the synapses weight can be altered by the relative timing of spikes across it. The synaptic weight with the memristor will be its conductance, and CMOS oscillator based circuits will be used to produce spikes that can modulate the memristor conductance by firing with different phases differences.

Intracranial pressure is an important parameter to monitor, and elevated intracranial pressure can be life threatening. Elevated intracranial pressure is indicative of distress in the brain attributed by conditions such as aneurysm, traumatic brain injury, brain tumor, hydrocephalus, stroke, or meningitis.

Electrocorticography (ECoG) recordings are invaluable in understanding epilepsy and detecting seizure zones. However, ECoG electrodes cause a foreign body mass effect, swelling, and pneumocephaly, which results in elevation of intracranial pressure (ICP). Thus, the aim of this work is to design an intracranial pressure monitoring system that could augment ECoG electrodes.

A minimally invasive, low-cost epidural intracranial pressure monitoring system is developed for this purpose, using a commercial pressure transducer available for biomedical applications. The system is composed of a pressure transducer, sensing cup, electronics, and data acquisition system. The pressure transducer is a microelectromechanical system (MEMS)-based die that works on piezoresistive phenomenon with dielectric isolation for direct contact with fluids.

The developed system was bench tested and verified in an animal model to confirm the efficacy of the system for intracranial pressure monitoring. The system has a 0.1 mmHg accuracy and a 2% error for the 0-10 mmHg range, with resolution of 0.01 mmHg. This system serves as a minimally invasive (2 mm burr hole) epidural ICP monitor, which could augment existing ECoG electrode arrays, to simultaneously measure intracranial pressure along with the neural signals.

This device could also be employed with brain implants that causes elevation in ICP due to tissue - implant interaction often leading to edema. This research explores the concept and feasibility for integrating the sensing component directly on to the ECoG electrode arrays.

Coarse Grain Reconfigurable Arrays (CGRAs) are promising accelerators capable of

achieving high performance at low power consumption. While CGRAs can efficiently

accelerate loop kernels, accelerating loops with control flow (loops with if-then-else

structures) is quite challenging. Techniques that handle control flow execution in

CGRAs generally use predication. Such techniques execute both branches of an

if-then-else structure and select outcome of either branch to commit based on the

result of the conditional. This results in poor utilization of CGRA s computational

resources. Dual-issue scheme which is the state of the art technique for control flow

fetches instructions from both paths of the branch and selects one to execute at

runtime based on the result of the conditional. This technique has an overhead in

instruction fetch bandwidth. In this thesis, to improve performance of control flow

execution in CGRAs, I propose a solution in which the result of the conditional

expression that decides the branch outcome is communicated to the instruction fetch

unit to selectively issue instructions from the path taken by the branch at run time.

Experimental results show that my solution can achieve 34.6% better performance

and 52.1% improvement in energy efficiency on an average compared to state of the

art dual issue scheme without imposing any overhead in instruction fetch bandwidth.

Fluxgate sensors are magnetic field sensors that can measure DC and low frequency AC magnetic fields. They can measure much lower magnetic fields than other magnetic sensors like Hall effect sensors, magnetoresistive sensors etc. They also have high linearity, high sensitivity and low noise. The major application of fluxgate sensors is in magnetometers for the measurement of earth's magnetic field. Magnetometers are used in navigation systems and electronic compasses. Fluxgate sensors can also be used to measure high DC currents. Integrated micro-fluxgate sensors have been developed in recent years. These sensors have much lower power consumption and area compared to their PCB counterparts. The output voltage of micro-fluxgate sensors is very low which makes the analog front end more complex and results in an increase in power consumption of the system. In this thesis a new analog front-end circuit for micro-fluxgate sensors is developed. This analog front-end circuit uses charge pump based excitation circuit and phase delay based read-out chain. With these two features the power consumption of analog front-end is reduced. The output is digital and it is immune to amplitude noise at the output of the sensor. Digital output is produced without using an ADC. A SPICE model of micro-fluxgate sensor is used to verify the operation of the analog front-end and the simulation results show very good linearity.