RISC-V Exceptions and Interrupts
Description
RISC-V is an open-source processor architecture developed by students and faculty at the University of California at Berkeley. This document explores RISC-V exceptions and interrupts by clarifying how this computer architecture handles traps. The document defines the different exceptions and interrupts outlined in the RISC-V architecture and explains the different registers that are used by the trap handler. This document also briefly addresses concepts outside the purview of the RISC-V ISA like interrupt controllers which are important for understanding how these external events interact with the processor hardware.
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2020-12
Agent
- Author (aut): Keller, Sean Richard
- Thesis director: Abraham, Seth
- Committee member: Brunhaver, John
- Contributor (ctb): Electrical Engineering Program
- Contributor (ctb): Barrett, The Honors College