Description
RISC-V is an open-source processor architecture developed by students and faculty at the University of California at Berkeley. This document explores RISC-V exceptions and interrupts by clarifying how this computer architecture handles traps. The document defines the different exceptions and interrupts outlined in the RISC-V architecture and explains the different registers that are used by the trap handler. This document also briefly addresses concepts outside the purview of the RISC-V ISA like interrupt controllers which are important for understanding how these external events interact with the processor hardware.
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Title
- RISC-V Exceptions and Interrupts
Contributors
- Keller, Sean Richard (Author)
- Abraham, Seth (Thesis director)
- Brunhaver, John (Committee member)
- Electrical Engineering Program (Contributor)
- Barrett, The Honors College (Contributor)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2020-12
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