Increasing the Efficiency of Heterogeneous System Operation: from Scheduling to Implementation of Split Federated Learning

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Description
This thesis addresses the problems of (a) scheduling multiple streaming jobs with soft deadline constraints to minimize the risk/energy consumption in heterogeneous Systems-on-chip (SoCs), and (b) training a neural network model with high accuracy and low training time using split

This thesis addresses the problems of (a) scheduling multiple streaming jobs with soft deadline constraints to minimize the risk/energy consumption in heterogeneous Systems-on-chip (SoCs), and (b) training a neural network model with high accuracy and low training time using split federated learning (SFL) with heterogeneous clients. Designing a scheduler for heterogeneous SoC SoCs built with different types of processing elements (PEs) is quite challenging, especially when it has to balance the conflicting requirements of low energy consumption, low risk, and high throughput for randomly streaming jobs at run time. Two probabilistic deadline-aware schedulers are designed for heterogeneous SoCs for such jobs with soft deadline constraints with the goals of optimizing job-level risk and energy efficiency. The key idea of the probabilistic scheduler is to calculate the task-to-PE allocation probabilities when a job arrives in the system. This allocation probability, generated by manually designed or neural network (NN) based allocation function, is used to compute the intra-job and inter-job contentions to derive the task-level slack. The tasks are allocated to the PEs that can complete the task within the task-level slack with minimum risk or minimum energy consumption. SFL is an edge-friendly decentralized NN training scheme, where the model is split and only a small client-side model is trained in the clients. The communication overhead in SFL is significant since the intermediate activations and gradients of every sample are transmitted in every epoch. Two communication reduction methods have been proposed, namely, loss-aware selective updating to reduce the number of training epochs and bottleneck layer (BL) to reduce the feature size.Next, the SFL system is trained with heterogeneous clients having different data rates and operating on non-IID data. The communication time of clients in low-end group with slow data rates dominates the training time. To reduce the training time without sacrificing accuracy significantly, HeteroSFL is built with HetBL and bi- directional knowledge sharing (BDKS). HetBL compresses data with different factors in low- and high-end groups using narrow and wide bottleneck layers respectively. BDKS is proposed to mitigate the label distribution skew across different groups. BDKS can also be applied in Federated Learning to address the label distribution skew.
Date Created
2023
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Design of a Self-Powered Global Positioning System (GPS)-Synchronized Micro-Continuous Point-on-Wave (CPoW) Module

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Description
The broad deployment of time-synchronized continuous point-on-wave (CPoW) modules will enable electric power utilities to gain unprecedented insight into the behavior of their power system assets, loads, and distributed renewable generation in real time. By increasing the available level of

The broad deployment of time-synchronized continuous point-on-wave (CPoW) modules will enable electric power utilities to gain unprecedented insight into the behavior of their power system assets, loads, and distributed renewable generation in real time. By increasing the available level of detail visible to operators, serious fault events such as wildfire-inducing arc flashes, safety-jeopardizing transformer failures, and equipment-damaging power quality decline can be mitigated in a data-driven, systematic manner. In this research project, a time-synchronized micro-scale CPoW module was designed, constructed, and characterized. This inductively powered CPoW module, which operates wirelessly by using the current flowing through a typical distribution conductor as its power source and a wireless data link for communication, has been configured to measure instantaneous line current at high frequency (nominally 3,000 samples per second) with 12-bit resolution. The design process for this module is detailed in this study, including background research, individual block design and testing, printed circuit board (PCB) design, and final characterization of the system. To validate the performance of this module, tests of power requirements, measurement accuracy, battery life, susceptibility to electromagnetic interference, and fault detection performance were performed. The results indicate that the design under investigation will satisfy the technical and physical constraints required for bulk deployment in an actual distribution network after manufacturing optimizations. After the test results were summarized, the future research and development activities needed to finalize this design for commercial deployment were identified and discussed.
Date Created
2021
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