In this work, the insight provided by our sophisticated Full Band Monte Carlo simulator is used to analyze the behavior of state-of-art devices like GaN High Electron Mobility Transistors and Hot Electron Transistors. Chapter 1 is dedicated to the description of the simulation tool used to obtain the results shown in this work. Moreover, a separate section is dedicated the set up of a procedure to validate to the tunneling algorithm recently implemented in the simulator. Chapter 2 introduces High Electron Mobility Transistors (HEMTs), state-of-art devices characterized by highly non linear transport phenomena that require the use of advanced simulation methods. The techniques for device modeling are described applied to a recent GaN-HEMT, and they are validated with experimental measurements. The main techniques characterization techniques are also described, including the original contribution provided by this work. Chapter 3 focuses on a popular technique to enhance HEMTs performance: the down-scaling of the device dimensions. In particular, this chapter is dedicated to lateral scaling and the calculation of a limiting cutoff frequency for a device of vanishing length. Finally, Chapter 4 and Chapter 5 describe the modeling of Hot Electron Transistors (HETs). The simulation approach is validated by matching the current characteristics with the experimental one before variations of the layouts are proposed to increase the current gain to values suitable for amplification. The frequency response of these layouts is calculated, and modeled by a small signal circuit. For this purpose, a method to directly calculate the capacitance is developed which provides a graphical picture of the capacitative phenomena that limit the frequency response in devices. In Chapter 5 the properties of the hot electrons are investigated for different injection energies, which are obtained by changing the layout of the emitter barrier. Moreover, the large signal characterization of the HET is shown for different layouts, where the collector barrier was scaled.

Semiconductor nanowires are important candidates for highly scaled three dimensional electronic devices. It is very advantageous to combine their scaling capability with the high yield of planar CMOS technology by integrating nanowire devices into planar circuits. The purpose of this research is to identify the challenges associated with the fabrication of vertically oriented Si and Ge nanowire diodes and modeling their electrical behavior so that they can be utilized to create unique three dimensional architectures that can boost the scaling of electronic devices into the next generation. In this study, vertical Ge and Si nanowire Schottky diodes have been fabricated using bottom-up vapor-liquid-solid (VLS) and top-down reactive ion etching (RIE) approaches respectively. VLS growth yields nanowires with atomically smooth sidewalls at sub-50 nm diameters but suffers from the problem that the doping increases radially outwards from the core of the devices. RIE is much faster than VLS and does not suffer from the problem of non-uniform doping. However, it yields nanowires with rougher sidewalls and gets exceedingly inefficient in yielding vertical nanowires for diameters below 50 nm. The I-V characteristics of both Ge and Si nanowire diodes cannot be adequately fit by the thermionic emission model. Annealing in forming gas which passivates dangling bonds on the nanowire surface is shown to have a considerable impact on the current through the Si nanowire diodes indicating that fixed charges and traps on the surface of the devices play a major role in determining their electrical behavior. Also, due to the vertical geometry of the nanowire diodes, electric field lines originating from the metal and terminating on their sidewalls can directly modulate their conductivity. Both these effects have to be included in the model aimed at predicting the current through vertical nanowire diodes. This study shows that the current through vertical nanowire diodes cannot be predicted accurately using the thermionic emission model which is suitable for planar devices and identifies the factors needed to build a comprehensive analytical model for predicting the current through vertically oriented nanowire diodes.

Solar energy, including solar heating, solar architecture, solar thermal electricity and solar photovoltaics, is one of the primary energy sources replacing fossil fuels. Being one of the most important techniques, significant research has been conducted in solar cell efficiency improvement. Simulation of various structures and materials of solar cells provides a deeper understanding of device operation and ways to improve their efficiency. Over the last two decades, polycrystalline thin-film Cadmium-Sulfide and Cadmium-Telluride (CdS/CdTe) solar cells fabricated on glass substrates have been considered as one of the most promising candidate in the photovoltaic technologies, for their similar efficiency and low costs when compared to traditional silicon-based solar cells. In this work a fast one dimensional time-dependent/steady-state drift-diffusion simulator, accelerated by adaptive non-uniform mesh and automatic time-step control, for modeling solar cells has been developed and has been used to simulate a CdS/CdTe solar cell. These models are used to reproduce transients of carrier transport in response to step-function signals of different bias and varied light intensity. The time-step control models are also used to help convergence in steady-state simulations where constrained material constants, such as carrier lifetimes in the order of nanosecond and carrier mobility in the order of 100 cm2/Vs, must be applied.

Since its inception about three decades ago, silicon on insulator (SOI) technology has come a long way to be included in the microelectronics roadmap. Earlier, scientists and engineers focused on ways to increase the microprocessor clock frequency and speed. Today, with smart phones and tablets gaining popularity, power consumption has become a major factor. In this thesis, self-heating effects in a 25nm fully depleted (FD) SOI device are studied by implementing a 2-D particle based device simulator coupled self-consistently with the energy balance equations for both acoustic and optical phonons. Semi-analytical expressions for acoustic and optical phonon scattering rates (all modes) are derived and evaluated using quadratic dispersion relationships. Moreover, probability distribution functions for the final polar angle after scattering is also computed and the rejection technique is implemented for its selection. Since the temperature profile varies throughout the device, temperature dependent scattering tables are used for the electron transport kernel. The phonon energy balance equations are also modified to account for inelasticity in acoustic phonon scattering for all branches. Results obtained from this simulation help in understanding self-heating and the effects it has on the device characteristics. The temperature profiles in the device show a decreasing trend which can be attributed to the inelastic interaction between the electrons and the acoustic phonons. This is further proven by comparing the temperature plots with the simulation results that assume the elastic and equipartition approximation for acoustic and the Einstein model for optical phonons. Thus, acoustic phonon inelasticity and the quadratic phonon dispersion relationships play a crucial role in studying self-heating effects.

This work is focused on modeling the reliability concerns in GaN HEMT technology. The two main reliability concerns in GaN HEMTs are electromechanical coupling and current collapse. A theoretical model was developed to model the piezoelectric polarization charge dependence on the applied gate voltage. As the sheet electron density in the channel increases, the influence of electromechanical coupling reduces as the electric field in the comprising layers reduces. A Monte Carlo device simulator that implements the theoretical model was developed to model the transport in GaN HEMTs. It is observed that with the coupled formulation, the drain current degradation in the device varies from 2%-18% depending on the gate voltage. Degradation reduces with the increase in the gate voltage due to the increase in the electron gas density in the channel. The output and transfer characteristics match very well with the experimental data. An electro-thermal device simulator was developed coupling the Monte Caro-Poisson solver with the energy balance solver for acoustic and optical phonons. An output current degradation of around 2-3 % at a drain voltage of 5V due to self-heating was observed. It was also observed that the electrostatics near the gate to drain region of the device changes due to the hot spot created in the device from self heating. This produces an electric field in the direction of accelerating the electrons from the channel to surface states. This will aid to the current collapse phenomenon in the device. Thus, the electric field in the gate to drain region is very critical for reliable performance of the device. Simulations emulating the charging of the surface states were also performed and matched well with experimental data. Methods to improve the reliability performance of the device were also investigated in this work. A shield electrode biased at source potential was used to reduce the electric field in the gate to drain extension region. The hot spot position was moved away from the critical gate to drain region towards the drain as the shield electrode length and dielectric thickness were being altered.

The drive towards device scaling and large output power in millimeter and sub-millimeter wave power amplifiers results in a highly non-linear, out-of-equilibrium charge transport regime. Particle-based Full Band Monte Carlo device simulators allow an accurate description of this carrier dynamics at the nanoscale. This work initially compares GaN high electron mobility transistors (HEMTs) based on the established Ga-face technology and the emerging N-face technology, through a modeling approach that allows a fair comparison, indicating that the N-face devices exhibit improved performance with respect to Ga-face ones due to the natural back-barrier confinement that mitigates short-channel-effects. An investigation is then carried out on the minimum aspect ratio (i.e. gate length to gate-to-channel-distance ratio) that limits short channel effects in ultra-scaled GaN and InP HEMTs, indicating that this value in GaN devices is 15 while in InP devices is 7.5. This difference is believed to be related to the different dielectric properties of the two materials, and the corresponding different electric field distributions. The dielectric effects of the passivation layer in millimeter-wave, high-power GaN HEMTs are also investigated, finding that the effective gate length is increased by fringing capacitances, enhanced by the dielectrics in regions adjacent to the gate for layers thicker than 5 nm, strongly affecting the frequency performance of deep sub-micron devices. Lastly, efficient Full Band Monte Carlo particle-based device simulations of the large-signal performance of mm-wave transistor power amplifiers with high-Q matching networks are reported for the first time. In particular, a CellularMonte Carlo (CMC) code is self-consistently coupled with a Harmonic Balance (HB) frequency domain circuit solver. Due to the iterative nature of the HB algorithm, this simulation approach is possible only due to the computational efficiency of the CMC, which uses pre-computed scattering tables. On the other hand, HB allows the direct simulation of the steady-state behavior of circuits with long transient time. This work provides an accurate and efficient tool for the device early-stage design, which allows a computerbased performance evaluation in lieu of the extremely time-consuming and expensive iterations of prototyping and experimental large-signal characterization.

In semiconductor physics, many properties or phenomena of materials can be brought to light through certain changes in the materials. Having a tool to define new material properties so as to highlight certain phenomena greatly increases the ability to understand that phenomena. The generalized Monte Carlo tool allows the user to do that by keeping every parameter used to define a material, within the non-parabolic band approximation, a variable in the control of the user. A material is defined by defining its valleys, energies, valley effective masses and their directions. The types of scattering to be included can also be chosen. The non-parabolic band structure model is used. With the deployment of the generalized Monte Carlo tool onto www.nanoHUB.org the tool will be available to users around the world. This makes it a very useful educational tool that can be incorporated into curriculums. The tool is integrated with Rappture, to allow user-friendly access of the tool. The user can freely define a material in an easy systematic way without having to worry about the coding involved. The output results are automatically graphed and since the code incorporates an analytic band structure model, it is relatively fast. The versatility of the tool has been investigated and has produced results closely matching the experimental values for some common materials. The tool has been uploaded onto www.nanoHUB.org by integrating it with the Rappture interface. By using Rappture as the user interface, one can easily make changes to the current parameter sets to obtain even more accurate results.