Thermal Management Techniques for 3D Heterogenous Integration of Semiconductor Packaging

The microelectronics industry is actively focusing on advanced packaging technologies, notably on three-dimensional stacking of heterogeneous integrated (3D-HI) circuits for enhanced performance. Despite its computational performance benefits, this approach faces challenges in thermal management due to increased power density and heat generation. Conventional cooling methods struggle to address this issue effectively. This study investigates microfluidic intralayer cooling techniques using analytical correlation and computational fluid dynamics (CFD) principles to propose a method capable of managing thermal performance across varying load conditions. The proposed configuration achieved a dissipation of 40 W/cm2 with a volumetric flow rate of 200 mL/min, maintaining chip temperature at 315K. Additionally, extreme hotspot conditions generating 1kW/cm2, along with the presence of thermal resistance from redistribution layers (RDLs), are analyzed. This research aims to establish a model for understanding geometric property variations under different heat flux conditions in 3D heterogeneous integration of semiconductor packaging.