Description
A fully automated logic design methodology for radiation hardened by design (RHBD) high speed logic using fine grained triple modular redundancy (TMR) is presented. The hardening techniques used in the cell library are described and evaluated, with a focus on both layout techniques that mitigate total ionizing dose (TID) and latchup issues and flip-flop designs that mitigate single event transient (SET) and single event upset (SEU) issues. The base TMR self-correcting master-slave flip-flop is described and compared to more traditional hardening techniques. Additional refinements are presented, including testability features that disable the self-correction to allow detection of manufacturing defects. The circuit approach is validated for hardness using both heavy ion and proton broad beam testing. For synthesis and auto place and route, the methodology and circuits leverage commercial logic design automation tools. These tools are glued together with custom CAD tools designed to enable easy conversion of standard single redundant hardware description language (HDL) files into hardened TMR circuitry. The flow allows hardening of any synthesizable logic at clock frequencies comparable to unhardened designs and supports standard low-power techniques, e.g. clock gating and supply voltage scaling.
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Details
Title
- Fully automated radiation hardened by design circuit construction
Contributors
- Hindman, Nathan (Author)
- Clark, Lawrence T (Thesis advisor)
- Holbert, Keith E. (Committee member)
- Barnaby, Hugh (Committee member)
- Allee, David (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2012
Subjects
Resource Type
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Note
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thesisPartial requirement for: Ph.D., Arizona State University, 2012
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bibliographyIncludes bibliographical references (p. 97-102)
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Field of study: Electrical engineering
Citation and reuse
Statement of Responsibility
by Nathan Hindman