Accelerator Design And Hardware Implementation For Distributed Coherent Mesh Beamformer

This dissertation summarizes achievements and ongoing designs of Field-Programmable Gate Array (FPGA) accelerators for Distributed Coherent Mesh Beamforming (DCMB). The goal of the distributed coherent network beamforming program is to create a network of distributed beams. The radios that make up this network must be small in size, weight, power, and cost while being able to overcome long transmission distances and interference. Due to the limitations, a solid communication link can be developed, using high speed to significantly increase signal strength and reduce interference. Two slots were developed to calculate the beamformer for the target platforms. One route is purely FPGA-based. Another option is a hybrid approach that uses the FPGA to do some of the initial calculations and the rest on the Central Processing Unit (CPU). Overall latency was significantly reduced when performing FPGA calculations. DCMB has become a technology for improving wireless communication systems, providing adaptability and efficiency in dynamic environments. This dissertation presents an in-depth study of DCMB with specific innovations in accelerator design and overall controller architecture. I investigate the design and implementation of dedicated accelerators adapted for DCMB tasks, including Finite Impulse Response (FIR) filtering, matrix multiplication, QR decomposition, and compensation on FPGA platforms. These accelerators are specially optimized for real-time processing and better performance on DCMB systems. Compared to soft-core processors, my research shows that hardware accelerators provide significantly faster processing speeds, enabling fast execution and reduced latency in communication systems. In addition, I discuss the design and integration of a general controller that optimizes the operation of accelerators and coordinates the beamforming process between distributed nodes. Through experiments with analytical and simulation tools, my study highlights the superiority of hardware accelerators over soft-core processors for high-speed calculation tasks in DCMB systems.