Impact of Variations, Measurement Uncertainty, and Surface Roughness on High-Speed Interconnect Validation

The rapid growth of emerging technologies is placing enormous demand on the seamless access to the extensive amount of data, which drives an unprecedented need for substantially higher data-transfer rates. As 1.6 Terabit Ethernet (TbE) specifications are being developed, high speed interconnects along with advanced materials and processes play a crucial role in technology enabling. However, validation of interconnect performance becomes increasingly challenging at these higher speeds. High-speed interconnect behavior can be reliably predicted if interconnect models are successfully validated against measurements. In industry, it is still not common practice to perform validation at actual use conditions. Therefore, there is an urge for a restructured design methodology and metrology based on temperature and humidity, to set realistic specs for high speed interconnects and reduce probability of failure under variations. Uncertainty quantification and propagation for interconnect validation is critical to assess the correlation quality more objectively, as well as to determine the bottleneck to improve the accuracy, repeatability and reproducibility of all the measurements involved in validation. The purpose of this work is to create a methodology that is both academically rigorous and has a significant impact on industry. This methodology provides an accurate characterization of the electrical performance of interconnects under realistic use-conditions, accompanied by an uncertainty analysis to improve the assessment of correlation quality. Part of this work contributed to the Packaging Benchmark Suite developed by IEEE EPS technical committee on electrical design, modeling, and simulation.