Sequential Circuit Temporal Hardening on an Advanced finFET Process

Microelectronic circuits are prone to upsets in the natural and manmade radiation environments. As the scaling of these circuits continues, they have become more susceptible to these upsets. In highly scaled technologies even the terrestrial radiation environment is becoming increasing source of soft errors in integrated circuits. Simultaneously the means of protecting circuits via the process technology have become more and more limited. As a result, design techniques to mitigate the upsets are becoming a requirement in an ever-growing list of applications. This work begins with an overview of radiation effects in integrated circuits. The phenomenology of upsets is discussed along with their basic mechanisms. How these effects are quantified in microelectronic circuits is then presented along with a summary of simulation methods. This is followed with a survey of the state of the field for radiation hardening by design techniques and a selection of radiation hardened flip flop designs. Upsets within these sequential circuits like flip flops can lead to process failure or erroneous execution and thus much of the radiation hardening effort is focused on protecting them. This work applies a systematic approach to radiation hardening by design to a temporally hardened flip flop and implements it in a 14nm finFET process. Forty-nine delay circuits are analyzed and compared on multiple performance metrics before a down select for integration. The resultant flip flop circuit is shown to have a minimum critical charge 3x higher than the baseline library flip flop. Physical design of the flip flop is outlined and nine configurations consisting of three delay lengths and three levels if bit interleaving are accomplished. The circuits are integrated as shift registers in a radiation test chip and exposed to heavy ion testing. Results of heavy ion testing demonstrate a threshold LET increase of approximately 6 MeV∙cm2/mg with marginal increases in saturation cross section for the target LET range. A failure mode is detected while storing ones, that has both area and time dependence. Substrate charge collection is suggested as a cause and a new circuit design is presented to mitigate the error with minimal performance impact.