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Title
Electron Microscopy Characterization of GaN-on-GaN Vertical Power Devices
Description
Wide bandgap semiconductors are of much current interest due to their superior electrical properties. This dissertation describes electron microscopy characterization of GaN-on-GaN structures for high-power vertical device applications. Unintentionally-doped (UID) GaN layers grown homoepitaxially via metal-organic chemical vapor deposition on freestanding GaN substrates, were subjected to dry etching, and layers of UID-GaN/p-GaN were over-grown. The as-grown and regrown heterostructures were examined in cross-section using transmission electron microscopy (TEM). Two different etching treatments, fast-etch-only and multiple etches with decreasing power, were employed. The fast-etch-only devices showed GaN-on-GaN interface at etched location, and low device breakdown voltages were measured (~ 45-95V). In comparison, no interfaces were visible after multiple etching steps, and the corresponding breakdown voltages were much higher (~1200-1270V). These results emphasized importance of optimizing surface etching techniques for avoiding degraded device performance.
The morphology of GaN-on-GaN devices after reverse-bias electrical stressing to breakdown was investigated. All failed devices had irreversible structural damage, showing large surface craters (~15-35 microns deep) with lengthy surface cracks. Cross-sectional TEM of failed devices showed high densities of threading dislocations (TDs) around the cracks and near crater surfaces. Progressive ion-milling across damaged devices revealed high densities of TDs and the presence of voids beneath cracks: these features were not observed in unstressed devices. The morphology of GaN substrates grown by hydride vapor-phase epitaxy (HVPE) and by ammonothermal methods were correlated with reverse-bias results. HVPE substrates showed arrays of surface features when observed by X-ray topography (XRT). All fabricated devices that overlapped with these features had typical reverse-bias voltages less than 100V at a leakage current limit of 10-6 A. In contrast, devices not overlapping with such features reached voltages greater than 300V. After etching, HVPE substrate surfaces showed defect clusters and macro-pits, whereas XRT images of ammonothermal substrate revealed no visible features. However, some devices fabricated on ammonothermal substrate failed at low voltages. Devices on HVPE and ammonothermal substrates with low breakdown voltages showed crater-like surface damage and revealed TDs (~25µm deep) and voids; such features were not observed in devices reaching higher voltages. These results should assist in developing protocols to fabricate reliable high-voltage devices.
Date Created
2021
Contributors
- Peri, Prudhvi Ram (Author)
- Smith, David J. (Thesis advisor)
- Alford, Terry (Committee member)
- Mccartney, Martha R (Committee member)
- Nemanich, Robert (Committee member)
- Zhao, Yuji (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
128 pages
Language
eng
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.2.N.161443
Level of coding
minimal
Cataloging Standards
Note
Partial requirement for: Ph.D., Arizona State University, 2021
Field of study: Materials Science and Engineering
System Created
- 2021-11-16 01:09:04
System Modified
- 2021-11-30 12:51:28
- 2 years 11 months ago
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