Full metadata
Title
WCET-aware scratchpad memory management for hard real-time systems
Description
Cyber-physical systems and hard real-time systems have strict timing constraints that specify deadlines until which tasks must finish their execution. Missing a deadline can cause unexpected outcome or endanger human lives in safety-critical applications, such as automotive or aeronautical systems. It is, therefore, of utmost importance to obtain and optimize a safe upper bound of each task’s execution time or the worst-case execution time (WCET), to guarantee the absence of any missed deadline. Unfortunately, conventional microarchitectural components, such as caches and branch predictors, are only optimized for average-case performance and often make WCET analysis complicated and pessimistic. Caches especially have a large impact on the worst-case performance due to expensive off- chip memory accesses involved in cache miss handling. In this regard, software-controlled scratchpad memories (SPMs) have become a promising alternative to caches. An SPM is a raw SRAM, controlled only by executing data movement instructions explicitly at runtime, and such explicit control facilitates static analyses to obtain safe and tight upper bounds of WCETs. SPM management techniques, used in compilers targeting an SPM-based processor, determine how to use a given SPM space by deciding where to insert data movement instructions and what operations to perform at those program locations. This dissertation presents several management techniques for program code and stack data, which aim to optimize the WCETs of a given program. The proposed code management techniques include optimal allocation algorithms and a polynomial-time heuristic for allocating functions to the SPM space, with or without the use of abstraction of SPM regions, and a heuristic for splitting functions into smaller partitions. The proposed stack data management technique, on the other hand, finds an optimal set of program locations to evict and restore stack frames to avoid stack overflows, when the call stack resides in a size-limited SPM. In the evaluation, the WCETs of various benchmarks including real-world automotive applications are statically calculated for SPMs and caches in several different memory configurations.
Date Created
2017
Contributors
- Kim, Yooseong (Author)
- Shrivastava, Aviral (Thesis advisor)
- Broman, David (Committee member)
- Fainekos, Georgios (Committee member)
- Wu, Carole-Jean (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
ix, 117 pages : color illustrations
Language
eng
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.42053
Statement of Responsibility
by Yooseong Kim
Description Source
Viewed on April 19, 2017
Level of coding
full
Note
thesis
Partial requirement for: Ph.D., Arizona State University, 2017
bibliography
Includes bibliographical references (pages 102-110)
Field of study: Computer science
System Created
- 2017-04-01 08:01:04
System Modified
- 2021-08-30 01:19:47
- 3 years 2 months ago
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