Description
As the number of cores per chip increases, maintaining cache coherence becomes prohibitive for both power and performance. Non Coherent Cache (NCC) architectures do away with hardware-based cache coherence, but they become difficult to program. Some existing architectures provide a middle ground by providing some shared memory in the hardware. Specifically, the 48-core Intel Single-chip Cloud Computer (SCC) provides some off-chip (DRAM) shared memory some on-chip (SRAM) shared memory. We call such architectures Hybrid Shared Memory, or HSM, manycore architectures. However, how to efficiently execute multi-threaded programs on HSM architectures is an open problem. To be able to execute a multi-threaded program correctly on HSM architectures, the compiler must: i) identify all the shared data and map it to the shared memory, and ii) map the frequently accessed shared data to the on-chip shared memory. This work presents a source-to-source translator written using CETUS that identifies a conservative superset of all the shared data in a multi-threaded application and maps it to the shared memory such that it enables execution on HSM architectures.
Details
Title
- Enabling multi-threaded applications on hybrid shared memory manycore architectures
Contributors
- Rawat, Tushar (Author)
- Shrivastava, Aviral (Thesis advisor)
- Dasgupta, Partha (Committee member)
- Fainekos, Georgios (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2014
Subjects
Resource Type
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Note
- thesisPartial requirement for: M.S., Arizona State University, 2014
- bibliographyIncludes bibliographical references (p. 46-48)
- Field of study: Computer science
Citation and reuse
Statement of Responsibility
by Tushar Rawat