Full metadata
Title
FPGA-based implementation of QR decomposition
Description
This thesis report aims at introducing the background of QR decomposition and its application. QR decomposition using Givens rotations is a efficient method to prevent directly matrix inverse in solving least square minimization problem, which is a typical approach for weight calculation in adaptive beamforming. Furthermore, this thesis introduces Givens rotations algorithm and two general VLSI (very large scale integrated circuit) architectures namely triangular systolic array and linear systolic array for numerically QR decomposition. To fulfill the goal, a 4 input channels triangular systolic array with 16 bits fixed-point format and a 5 input channels linear systolic array are implemented on FPGA (Field programmable gate array). The final result shows that the estimated clock frequencies of 65 MHz and 135 MHz on post-place and route static timing report could be achieved using Xilinx Virtex 6 xc6vlx240t chip. Meanwhile, this report proposes a new method to test the dynamic range of QR-D. The dynamic range of the both architectures can be achieved around 110dB.
Date Created
2014
Contributors
- Yu, Hanguang (Author)
- Bliss, Daniel W (Thesis advisor)
- Ying, Lei (Committee member)
- Chakrabarti, Chaitali (Committee member)
- Arizona State University (Publisher)
Topical Subject
Resource Type
Extent
ix, 86 p. : ill. (some col.)
Language
eng
Copyright Statement
In Copyright
Primary Member of
Peer-reviewed
No
Open Access
No
Handle
https://hdl.handle.net/2286/R.I.24870
Statement of Responsibility
by Hanguang Yu
Description Source
Viewed on July 11, 2014
Level of coding
full
Note
thesis
Partial requirement for: M.S., Arizona State University, 2014
bibliography
Includes bibliographical references (p. 84-86)
Field of study: Electrical engineering
System Created
- 2014-06-09 02:08:58
System Modified
- 2021-08-30 01:35:36
- 3 years 2 months ago
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