Description
In thesis, a test time reduction (a low cost test) methodology for digitally-calibrated pipeline analog-to-digital converters (ADCs) is presented. A long calibration time is required in the final test to validate performance of these designs. To reduce total test time, optimized calibration technique and calibrated effective number of bits (ENOB) prediction from calibration coefficient will be presented. With the prediction technique, failed devices can be identified only without actual calibration. This technique reduces significant amount of time for the total test time.
Details
Title
- Digital calibration and prediction of effective number of bits for pipeline ADC
Contributors
- Kim, Kibeom (Author)
- Ozev, Sule (Thesis advisor)
- Kitchen, Jennifer (Committee member)
- Barnaby, Hugh (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2013
Subjects
Resource Type
Collections this item is in
Note
- thesisPartial requirement for: M.S., Arizona State University, 2013
- bibliographyIncludes bibliographical references (p. 22-23)
- Field of study: Electrical engineering
Citation and reuse
Statement of Responsibility
by Kibeom Kim