Description
The existing compact models can reproduce the characteristics of MOSFETs in the temperature range of -40oC to 125oC. Some applications require circuits to operate over a wide temperature range consisting of temperatures below the specified range of existing compact models, requiring wide temperature range compact models for the design of such circuits. In order to develop wide temperature range compact models, fourteen different geometries of n-channel and p-channel MOSFETs manufactured in a 0.18μm mixed-signal process were electrically characterized over a temperature range of 40 K to 298 K. Electrical characterization included ID-VG and ID-VD under different drain, body and gate biases respectively. The effects of low-temperature operation on the performance of 0.18μm MOSFETs have been studied and discussed in terms of sub-threshold characteristics, threshold voltage, the effect of the body bias and linearity of the device. As it is well understood, the subthreshold slope, the threshold voltage, drive currents of the MOSFETs increase when the temperature of the MOSFETs is lowered, which makes it advantageous to operate the MOSFETs at low-temperatures. However the internal linearity gm1/gm3 of the MOSFETs degrades as the temperature of the MOSFETs is lowered, and the performance of the MOSFETs can be affected by the interface traps that exist in higher density close to conduction band and valence band energy levels, as the Fermi-level moves closer to bandgap edges when MOSFETs are operated at cryogenic temperatures.
Details
Contributors
- Kathuria, Achal (Author)
- Barnaby, Hugh (Thesis advisor)
- Schroder, Dieter K. (Committee member)
- Vermeire, Bert (Committee member)
- Arizona State University (Publisher)
Date Created
The date the item was original created (prior to any relationship with the ASU Digital Repositories.)
2010
Topical Subject
Resource Type
Language
- eng
Note
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thesisPartial requirement for: M.S., Arizona State University, 2010
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Includes bibliographical references (p
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Field of study: Electrical engineering
Citation and reuse
Statement of Responsibility
by Achal Kathuria
Additional Information
Extent
- xii, 64 p. : ill. (some col.)